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  1. picorv32 picorv32 Public

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    PicoRV32 - A Size-Optimized RISC-V CPU

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  3. openmsp430 openmsp430 Public

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    The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.

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  4. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  5. LLVIP LLVIP Public

    Forked from bupt-ai-cz/LLVIP

    LLVIP: A Visible-infrared Paired Dataset for Low-light Vision

    Jupyter Notebook

  6. Learning-to-See-in-the-Dark Learning-to-See-in-the-Dark Public

    Forked from cchen156/Learning-to-See-in-the-Dark

    Learning to See in the Dark. CVPR 2018

    Python