Tags: analogdevicesinc/linux
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Here's the pile of clk driver patches. The usual suspects^Wsilicon vendors are all here, adding new SoC support and fixing existing code. There are a few patches to the clk framework here as well. They've been baking in linux-next for weeks so I'm hoping we don't have to revert them. The disable OF node patch is probably the scariest one although it seems unlikely that a system would be relying on a driver _not_ probing because the clk never appeared, but you never know. Nothing looks out of the ordinary on the driver side but that's because it's mostly a bunch of data. Core: - Use dev_err_probe() in the clk registration path (Peering into the crystal ball shows many patches that remove printks) - Check for disabled OF nodes in of_clk_get_hw_from_clkspec() New Drivers: - Allwinner A523/T527 clk driver - Qualcomm IPQ9574 NSS clk driver - Qualcomm QCS8300 GPU and video clk drivers - Qualcomm SDM429 RPM clks - Qualcomm QCM6490 LPASS (low power audio) resets - Samsung Exynos2200: driver for several clock controllers (Alive, CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS) - Samsung Exynos7870: Driver for several clock controllers (Alive, MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI) - Rockchip rk3528 and rk3562 clk driver Updates: - Various fixes to SoC clk drivers for incorrect data, avoid touching protected registers, etc. - Additions for some missing clks in existing SoC clk drivers - DT schema conversions from text to YAML - Kconfig cleanups to allow drivers to be compiled on moar architectures
arm64: boot: xilinx: jupiter: specify shunt resistor value Specify the external shunt resistor value for properly display the current and the power. Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
A few clk driver fixes for Samsung and Qualcomm clk drivers - Suspend on Google GS101 crashes when trying to save some clk registers that we shouldn't be saving so we don't do that anymore - The PLL lock time was wrong on the Tesla FSD which could lead to the PLL never locking - Qualcomm's display clk controller on SM8750 was trying to change the frequency of a parent clk for the DSI device when it should have stopped and adjusted the divider. The failure is that the clk frequency was half what was expected, leading to broken display.
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