AD9172: implement NCO phase alignment on SYSREF edge #3095
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Add support for NCO reset via SYSREF for phase coherency across links, and also devices in case of subclass 1 operation. Add sequence described in [1], and provided by AD customer support. The steps of the sequence, or registers are currently not described in datasheet rev C of ad917x. [1] https://ez.analog.com/data_converters/high-speed_dacs/f/q-a/541162/synchronizing-phases-of-dac0-and-dac1-in-ad9173-nco-only-mode/417612 Co-developed-by: Jukka Hynninen <jukka.hynninen@vaisala.com> Signed-off-by: Jukka Hynninen <jukka.hynninen@vaisala.com> Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Lane rate unit should be in bits per second, instead of bytes per second as currently printed out. Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
Avoid disabling channels/dac paths that might be enabled by user. Since the integration to JESD FSM framework, channels or main data paths might have been enabled by user at point when function is run. This is particularly the case, if FSM stop-states are used to pause operation at certain checkpoints. State information will contain up-to-date configuration, so use that as a reference. Add missing return value check while at it. Signed-off-by: Tomas Melin <tomas.melin@vaisala.com>
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Any ideas what is wrong with the build tests? |
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AD9172: implement NCO phase alignment on SYSREF edge
Add support for NCO reset via SYSREF for phase coherency across links, and also devices, in case of subclass 1 operation.
Add sequence described and provided by AD customer support. See commit messages for further details.
This has been primarily developed and tested on our hardware. I have also sanity tested these changes on zcu102 with ad9172 eval kit. Default setting for that version is single link so verifying actual phase coherency was not trivial on that hardware.
Signed-off-by: Tomas Melin tomas.melin@vaisala.com
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