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1. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

   SystemVerilog

2. cocotb cocotb Public

   Forked from cocotb/cocotb

   cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

   Python

3. riscv-dv riscv-dv Public

   Forked from chipsalliance/riscv-dv

   SV/UVM based instruction generator for RISC-V processor verification

   Python 1

4. core-v-verif core-v-verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly