Refer to Final Circuit.circ logisim file to load the processor onto logisim. Implementation Circuit.pdf contains details on each of the components in the procesor.Instruction Encoding.pdf contains the naive ISA design used.
Note that the only similarity to RISC pipeline is the classic 5 stage pipeline. We have not implemented the exact ISA (privileged or unprivileged) and other specs like zicr and CSR registers.
This project implements a five-stage 32-bit pipeline with a simplified instruction set. The pipeline includes:
- A hardwired control unit.
- A dual-port register unit with 32 general-purpose registers (GPRs).
- 24-bit wide memory addresses (maximum size usable in Logisim).
- 32-bit wide data paths.
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Reset the Circuit
Click the reset button or pressCtrl + Rto reset the circuit to its default configuration. -
Set Stage Counter
Manually set the counter to4(this implies that stage 5 is complete), so the pipeline starts afresh from stage 1.- Right-click the control unit to access and modify the counter.
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Load Instructions
- Use the poke tool to access memory.
- Load instructions using a memory image (
Load Imageoption). - Instructions can start from any base address.
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Set Program Counter (PC)
- Using the poke tool, double-click the fetch unit and set the PC to the base address of the first instruction.
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Start Execution
- Press
Ctrl + Kto enable the clock trigger and begin execution.
- Press
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Run Until Halt
- Wait until the
Haltinstruction is executed. - Once the halt instruction is encountered, the stage counter stops, indicating completion.
- Wait until the
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View Results
- Results can be viewed at specific RAM addresses, depending on the program being executed.
The processor supports the following instructions and their immediate value versions:
ADD,SUB,MOVE,LOAD,STORE,OR,AND,HALTBranching and branch prediction may be added in later revision.
- The memory address size is restricted by Logisim to 24 bits.
- Ensure your program includes a
Haltinstruction for proper termination.