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croc
croc PublicForked from sislab-vnu/croc
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
SystemVerilog
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cve2
cve2 PublicForked from openhwgroup/cve2
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
SystemVerilog
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