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1. Busmaster_CANSocket Busmaster_CANSocket Public

   Busmaster komunikacija/ BUSMASTER-CANSocket (RPi)

   C

2. 4-bit-dac 4-bit-dac Public

   Verilog

3. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

4. core-v-verif core-v-verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly

5. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog

6. palace-aws-demo palace-aws-demo Public

   Forked from LubomirJagos42/palace-aws-demo

   Running palace AWD demo projects for EM simulations which are verified.

   Python