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EmJunaid/README.md

Hi, I’m a Digital Design Engineer with around 4 years of RTL design experience, specializing in RISC-V based CPU and SoC design and the design of custom hardware accelerators for compute-intensive algorithms. Experienced across the full flow, from microarchitecture to RTL, FPGA prototyping, simulation-based verification, phsical design and silicon bring-up. Comfortable bridging hardware and baremetal firmware to validate designs on real silicon. You can reach me through writing an email to me at: junaidamjad543@gmail.com

Popular repositories Loading

  1. RISC-V-32I-5-stage-Pipeline-Processor RISC-V-32I-5-stage-Pipeline-Processor Public

    5 stage pipeline implementation of RISC-V 32I Processor.

    Verilog 16 2

  2. Risc-V-32I-Single-Cycle-Processor Risc-V-32I-Single-Cycle-Processor Public

    Implementation of RiscV single cycle architecture consisting of six base instructions (R, I, B, S, J, U).

    Verilog 1 2

  3. EmJunaid EmJunaid Public

    Config files for my GitHub profile.

  4. CSRs_Implementation CSRs_Implementation Public

    Verilog

  5. Database Database Public

  6. Matrix-Multiplier-FSM Matrix-Multiplier-FSM Public

    Takes two 10x10 matrices stored in two different 1rw memories and calculate result through repetitive addition and store resultant matrix C back in 1r1w memory.

    Verilog