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mio_digital_design_project_template
mio_digital_design_project_template Public templateDTC Digital Design Project Template
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core-v-verif
core-v-verif PublicForked from openhwfoundation/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
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core-v-mcu
core-v-mcu PublicForked from openhwfoundation/core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
SystemVerilog 1
Repositories
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Simple UVM environment for experimenting with Verilator.
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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
- core-v-verif Public Forked from openhwfoundation/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
- verilator-uvm-example Public Forked from antmicro/verilator-uvm-example
Example of how to use UVM with Verilator
- neorv32 Public Forked from stnolting/neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
- verilog-ethernet Public Forked from alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
- taxi Public Forked from fpganinja/taxi
AXI, AXI stream, Ethernet, and PCIe components in System Verilog
- ethernet-fmc-taxi-eth Public Forked from fpgadeveloper/ethernet-fmc-taxi-eth
Reference designs for the Opsero Ethernet FMC based on the open-source Taxi transport library
- core-v-mcu Public Forked from openhwfoundation/core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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