Skip to content
View ArjunPShetty's full-sized avatar
💫
Checkmate
💫
Checkmate

Block or report ArjunPShetty

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. RISC-V_CPU RISC-V_CPU Public

    A custom 32-bit RISC processor implemented in Verilog, demonstrating datapath, control logic, and instruction execution.

    Verilog 7 8

  2. Verilog Verilog Public

    A collection of basic to intermediate Verilog and RTL design examples created for learning digital design, RTL coding, and hardware description concepts.

    Verilog 5 2

  3. Lumo Lumo Public

    LUMO is a voice-controlled home automation system using NodeMCU and Python code to control lights and fans with real-time feedback and Wi-Fi connectivity.

    Python 5 1

  4. Single_Cycle_RISC-V Single_Cycle_RISC-V Public

    This project implements a RISC-V Single-Cycle processor in Verilog, integrating PC, ALU, register file, control, and memory into a simple reference CPU design.

    Verilog 5 2

  5. UART_TX-RX UART_TX-RX Public

    A Verilog-based full-duplex UART transmitter and receiver with configurable baud rate and serial-to-parallel data conversion.

    Verilog 4 3

  6. Asynchronous-FIFO Asynchronous-FIFO Public

    A Verilog asynchronous FIFO using Gray-coded pointers for safe clock domain crossing and reliable full/empty detection.

    Verilog 2