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1. Physical-Implementation-of-CORE-V-CV32E40P-RISC-V-IP Physical-Implementation-of-CORE-V-CV32E40P-RISC-V-IP Public

   A complete ASIC implementation of the CV32E40P RISC-V core from OpenHW Group, covering RTL synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure and DFT insertion

   Verilog 5 6

2. RTL-to-GDS-Implementation-of-Low-Power-Configurable-Multi-Clock-Digital-System RTL-to-GDS-Implementation-of-Low-Power-Configurable-Multi-Clock-Digital-System Public

   A project that covers efficient RTL design, low-power techniques, multi-clock management, synthesis, static timing analysis, self-checking testbench, DFT insertion, and post-layout analysis, encomp…

   Verilog 7 1

3. RISC-V-From-Single-Cycle-to-Pipelined-Implementation RISC-V-From-Single-Cycle-to-Pipelined-Implementation Public

   RISC-V processor transitioning from a single-cycle design to a pipelined implementation with hazard detection

   Verilog

4. Hardware-Software-Co-Design-of-AES-Encryption-using-Nios-V-Processor Hardware-Software-Co-Design-of-AES-Encryption-using-Nios-V-Processor Public

   HW/SW co-design of AES encryption using a Nios V processor on a Cyclone V FPGA. The AES core is integrated via a custom AXI4-Lite wrapper for efficient hardware acceleration and control from software

   SystemVerilog 1 1

5. VHDL VHDL Public

   Library for VHDL designs including 8-bit Microprocessor mini project

   VHDL 1

6. ITS-EM ITS-EM Public

   Jupyter Notebook