Questions tagged [stack-up]
The stack-up tag has no summary.
85 questions
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Layer order of a four layer stackup suited to several different high speed digital interfaces
I have encountered a tow road selecting the order of layers in a 4-L stackup. Please consider the pcb has rmii, 2 x usb 2 full speed, qspi, sd card, and a tft controller parallel interface. Several ...
- 67
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Is it acceptable to have a power plane coupled to a signal layer in a 6-layer stackup?
I'm working on a 6-layer rigid-flex analog signal instrumentation node board. It rectifies and amplifies a 40kHz transducer, clamps it to 2.5V, turns it into a differential pair, and ships it back ...
- 37
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PCB stackup for EMI-noisy environments
I am planning 6 layers PCB stackup for a product that will operate in very EMI noisy environments. The maximum speed on digital traces will be 50 MHz. I am planning the following stack-up
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- 497
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Why do different PCB manufacturers have different standard stackups?
I am designing a PCB. My PCB has controlled impedance traces for PCIe and 1G Ethernet signals.
I looked up the 6-layer stackup specification for my board house. I used their stackup information with a ...
- 1,510
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High-frequency routing with GND–Signal–GND stackup: Can two signals share the same physical path in adjacent layers?
I’m working with high-frequency signal routing and I have a question about return currents in multilayer PCB stackups.
Let’s say I have a typical stripline configuration with a GND–Signal–GND sandwich....
- 79
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Board stackup dimension calculation
I am trying to design a PCB in KiCAD using the antenna described in Texas Instruments' Application Note 043. The note reads (p4):
It is also recommended to use the same thickness and type of PCB ...
- 197
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104
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High speed PCB design questions
I am senior EE student and working towards high speed PCB board design including DDR3, Gigabit Ethernet, MIPI and HDMI. I finally completed schematic and moving towards PCB design. As expected, I am ...
- 359
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Ground bounce on a PCB Plane
Suppose in my PCB, due to ground bounce, the voltage on the reference plane of a PCB, for example, increases by, say 0.2 V.
In the PCB stackup, the ground plane (or return plane) is typically a ...
- 1,827
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HDI stack up optimization
Regarding a very dense and complicated design, with several fine pitch BGAs, I have the following issue. This pictures shows the stack up for my PCB manufactures as my HDI stack up for 14 layers:
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- 1,438
2
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1
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Flip chip assembly consideration in PCB stack up
In the following 14 layer PCB, there is a flip chip assembly for one of the chips, the chips is very fine pitch around 200 um:
Considering that in flip-chip assembly, the heating process occurs from ...
- 1,438
3
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Blind and buried via rules definition for HDI design
I want to define the following rules for my HDI PCB and the PCB is a 14 layer stack up and this is my HDI microvia stack up:
I want to define:
If it is buriedvia, then Via Hole Size:0.15 mm and Via ...
- 1,438
2
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84
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In Altium, how can I add a second layer of solder resist?
I would like to have PCBs manufactures with two layers of solder resist. I have been in contact with my manufacturer, and they say this is fine: just add it to the layer stack, and mention it in the ...
- 28k
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2
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282
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Is this the correct way to calculate the Impedance trace to copper?
I am building a PCB that has an USB Type-C connected to an STM32F405RGT6. I used the impedance calculator tool from JLCPCB(I order from them) to figure out the width of the traces and the stack up ...
- 497
1
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2
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How to calculate stripline asymmetric impedance on Saturn PCB toolkit?
I am designing a PCB layout. This PCB contains 75 ohm video traces. Also, these traces only give output from the connector to another connector. When I make a calculation in the stripline asymmetric ...
- 129
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Layer stack up selection for better signal integrity
I need to find an optimized stack up from the signal integrity point of view. I want provide for all of my signal tracks an adjacent GND plane. I have the following candidates for my stack up, would ...
- 1,438