Questions tagged [sequence-detector]
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40 questions
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Designing an Overlapping Mealy FSM to Detect the Pattern D–X–B–B
1. Problem Statement
Design a synchronous Mealy finite-state machine that scans a continuous stream of letters (A, B, C, D) encoded in two bits and asserts y=1 only ...
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"11" overlapping sequence detector using mealy machine
Design a sequence detector that detects two or more consecutive 1’s in an input stream of bits (as in 01110111100) using a Mealy machine and T flip flop.
I have made the state diagram and the final ...
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2
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Design of a FSM two input detector sequence
I'm designing a finite state machine (FSM) that detects the sequences "01011" and "00101" in a serial binary input. When either sequence is detected, the FSM should output (Y1, Y2) ...
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Moore Detector -1011, non-overlapping case
I am not able to figure out why the output goes low when I have done it properly. I used the similar logic for Mealy. It worked, but here it's not proper.
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Mealy FSM using SR Flip Flops: pattern detector
I was asked to design a Mealy FSM using SR Flip Flops to detect a pattern.
It should detect if the pattern is either '1001' or '0110'.
I was able to make the state diagram (I have attached the image), ...
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Design of non-overlapping "1010" sequence detector
Assuming that A, B, C and D are the four states. When detecting the sequence "1010", in the D state, if overlapping is not allowed, we have the following state diagram:
After detecting "...
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For a simple sequence detector, is there a problem with the FSM diagram for unused states?
This is the diagram, and the sequence we are detecting is 1011. The problem did not specify whether it is Mealy or Moore FSM, or whether it is overlapping or non-overlapping.
When we get an input of ...
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Is this Mealy FSM representation correct for 00111? [closed]
Is this Mealy FSM representation correct for a non-overlapping input bit sequence detector for the sequence 00111?
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Sequence detector which detects sequences 100 and 111
I need to design a pattern detector that recognizes 100 and 111 bit patterns, even overlapping ones. I drew the state diagram as shown in the image
and created the related table
Could you tell me if ...
2
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1
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152
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Is this a correct FSM graph?
This question is sourced from H. Roth's book 'Fundamentals of Logic Design.' It pertains to a sequential circuit featuring a single input (X) and one output (Z). The circuit's function entails ...
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Syntax error Begin statement HDL 9-806
I have an error in the form of HDL 9-806 on the begin statement.
The code below is a button based sequence detector an addition LED flash when sequence is correct with a debouncer to stop multiple ...
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100011 Sequence detector using 1 bit
i made the 100011 sequence detector state diagram like this it's in link. Is it kinda true ? I am new in this topic. After this step I am going to do verilog implementation
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0110 Moore FSM overlapping in Verilog
I am designing "0110" overlapping sequence detector using Moore FSM model in Verilog.
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Is this state machine correct for a Mealy 4b'1001 sequence detector?
Is this a correct state machine diagram for detecting the 4-bit sequence 4b'1001 using a non-overlapping Mealy FSM? If any bit is out of sequence, reset to the initial state. Once the last bit of the ...
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Why does sequence detector for 1100 show the correct output for all input 1100 sequences except one in the beginning?
The code I am using is the following. I am using five states as this is a Moore model, and non-overlapping sequence is assumed. The state logic is correct as far as I can tell. However, when I run it, ...
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