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I just wanna ask about the rest push button connection. Are there technological reasons for making it active low and not active high?

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    \$\begingroup\$ We can't know that. Some MCUs have active low reset and some have active high, and that's it. \$\endgroup\$ Commented Nov 11 at 14:53
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    \$\begingroup\$ what difference does it make? \$\endgroup\$ Commented Nov 11 at 15:17
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    \$\begingroup\$ electronics.stackexchange.com/questions/7664/… \$\endgroup\$ Commented Nov 11 at 15:25
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    \$\begingroup\$ @G36 that accepted answer of your link does not even answer the asked question. It is just as easy to keep reset at VCC with a capacitor than it is to keep reset at GND with a capacitor, until a resistor charges it to the other potential. As a question, this is a duplicate as far as I see. \$\endgroup\$ Commented Nov 11 at 15:28
  • \$\begingroup\$ active-low (ie common drain) in general = pretty foolproof when driving it from another power zone (but same GND) \$\endgroup\$ Commented Nov 11 at 18:13

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"Historical Reasons", I guess.

Other microcontroller families have positive resets; a NRST might a tiny bit easier to drive with an open drain / collector output, but frankly, why that would be a factor for a reset pin, I can't really find.

Someone, somewhere, started implementing this thing with a low-active reset, and then the other designers stuck with it. Where these "original culprits" here worked is hard to tell – for example, ARMJTAG does specify a nTRST pin, so probably arm is responsible for nudging ST in that direction, but JTAG and ARM are about equally old, so it's likely that someone from the original JTAG committee said "oh let's prefer low-active reset". And now we're in the early 1980's, with their own technical restrictions, which are different than they were when STM32 got introduced.

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    \$\begingroup\$ Maybe the thought process was along the lines of different voltage rails needed, pulling it to GND with an open collector / drain might be that tiny bit easier than pulling it to the correct VCC level (which might not be stable because you created a short circuit in your program) or something. You can also have multiple devices on your nRST like a watchdog and the debugger. \$\endgroup\$ Commented Nov 11 at 15:52
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    \$\begingroup\$ The STM32 actually often has an open drain output on the reset pin - so that on chip reset generators (e..g watchdog) can also automatically reset external hardware if needed. Also in the distant past, strapping an input pin of TTL logic directly to +5V could result in a latchup of the chip, always recommended a pullup resistor : also ground is a common voltage even on multiple Vdd implementations - grounding a pin is "safer" than connecting it to some random Vdd that may cause protection diodes to conduct. But yes the 8051 is active high reset for instance .. \$\endgroup\$ Commented Nov 12 at 9:05
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    \$\begingroup\$ @Velvet Not sure a soft-processor counts, but the MicroBlaze Reset says "Both external reset signals are active-High, and it is recommended to assert the signals for at least 16 cycles" \$\endgroup\$ Commented Nov 12 at 9:12
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    \$\begingroup\$ @Velvet the og 8051, the intel MCS-51 family, hat positive reset, "MCS-51 microcontroller family user's manual", 1194 ed., p. 3-26 (PDF page 134). I think that one might actually be pretty important! It's easy to find 15 families with low-active resets, for the reasons mentioned in my answer: everyone uses JTAG, JTAG standardizes NRST, it would be annoying not to do the same. Note that (surprisingly, maybe), the intel 8080 microprocessor has an active-low reset. So, probably, even within the same company with likely the same designers on NMOS, things aren't consistent, which indicates… \$\endgroup\$ Commented Nov 12 at 10:39
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    \$\begingroup\$ … that technical reasons on the chip side are likely not the driving force here! It's likely "what the customer expects" that's driving this. \$\endgroup\$ Commented Nov 12 at 10:40

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