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feat!: bump QEMU to 5.1.0 #2143

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cb48981
feat!: update QEMU core to 5.1.0
amaanq Apr 6, 2025
fe0e980
feat!: update FPU to 5.1.0
amaanq Apr 6, 2025
1a30d07
feat!: update TCG to 5.1.0
amaanq Apr 6, 2025
52ac072
feat!: update ARM to 5.1.0
amaanq Apr 6, 2025
220332e
feat!: update i386 to 5.1.0
amaanq Apr 6, 2025
deac5a8
feat!: update M68K to 5.1.0
amaanq Apr 6, 2025
b6306df
feat!: update MIPS to 5.1.0
amaanq Apr 6, 2025
515d513
feat!: update PPC to 5.1.0
amaanq Apr 6, 2025
20ad653
feat!: update RISC-V to 5.1.0
amaanq Apr 6, 2025
cd7a831
feat!: update S390X to 5.1.0
amaanq Apr 6, 2025
4a6d59d
feat!: update SPARC to 5.1.0
amaanq Apr 6, 2025
1faafcb
feat!: updatae TriCore to 5.1.0
amaanq Apr 6, 2025
d3c96df
build: update CMake files & symbols
amaanq Apr 6, 2025
6de42c7
feat!: update architecture headers
amaanq Apr 6, 2025
4595bde
feat!: update bindings
amaanq Apr 6, 2025
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4 changes: 4 additions & 0 deletions CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -568,6 +568,7 @@ add_library(arm-softmmu STATIC
qemu/target/arm/helper.c
qemu/target/arm/iwmmxt_helper.c
qemu/target/arm/m_helper.c
qemu/target/arm/mte_helper.c
qemu/target/arm/neon_helper.c
qemu/target/arm/op_helper.c
qemu/target/arm/psci.c
Expand Down Expand Up @@ -612,6 +613,7 @@ add_library(aarch64-softmmu STATIC
qemu/target/arm/helper.c
qemu/target/arm/iwmmxt_helper.c
qemu/target/arm/m_helper.c
qemu/target/arm/mte_helper.c
qemu/target/arm/neon_helper.c
qemu/target/arm/op_helper.c
qemu/target/arm/pauth_helper.c
Expand Down Expand Up @@ -1019,6 +1021,7 @@ add_library(riscv32-softmmu STATIC
qemu/target/riscv/pmp.c
qemu/target/riscv/translate.c
qemu/target/riscv/unicorn.c
qemu/target/riscv/vector_helper.c
)

if(MSVC)
Expand Down Expand Up @@ -1052,6 +1055,7 @@ add_library(riscv64-softmmu STATIC
qemu/target/riscv/pmp.c
qemu/target/riscv/translate.c
qemu/target/riscv/unicorn.c
qemu/target/riscv/vector_helper.c
)

if(MSVC)
Expand Down
6 changes: 4 additions & 2 deletions bindings/dotnet/UnicornEngine/Const/Mips.fs
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Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,10 @@ module Mips =
let UC_CPU_MIPS64_I6500 = 9
let UC_CPU_MIPS64_LOONGSON_2E = 10
let UC_CPU_MIPS64_LOONGSON_2F = 11
let UC_CPU_MIPS64_MIPS64DSPR2 = 12
let UC_CPU_MIPS64_ENDING = 13
let UC_CPU_MIPS64_LOONGSON_3A1000 = 12
let UC_CPU_MIPS64_LOONGSON_3A4000 = 13
let UC_CPU_MIPS64_MIPS64DSPR2 = 14
let UC_CPU_MIPS64_ENDING = 15

// MIPS registers

Expand Down
12 changes: 7 additions & 5 deletions bindings/dotnet/UnicornEngine/Const/Riscv.fs
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Expand Up @@ -10,15 +10,17 @@ module Riscv =
// RISCV32 CPU

let UC_CPU_RISCV32_ANY = 0
let UC_CPU_RISCV32_BASE32 = 1
let UC_CPU_RISCV32_SIFIVE_E31 = 2
let UC_CPU_RISCV32_SIFIVE_U34 = 3
let UC_CPU_RISCV32_ENDING = 4
let UC_CPU_RISCV32_BASE = 1
let UC_CPU_RISCV32_IBEX = 2
let UC_CPU_RISCV32_SIFIVE_E31 = 3
let UC_CPU_RISCV32_SIFIVE_E34 = 4
let UC_CPU_RISCV32_SIFIVE_U34 = 5
let UC_CPU_RISCV32_ENDING = 6

// RISCV64 CPU

let UC_CPU_RISCV64_ANY = 0
let UC_CPU_RISCV64_BASE64 = 1
let UC_CPU_RISCV64_BASE = 1
let UC_CPU_RISCV64_SIFIVE_E51 = 2
let UC_CPU_RISCV64_SIFIVE_U54 = 3
let UC_CPU_RISCV64_ENDING = 4
Expand Down
6 changes: 4 additions & 2 deletions bindings/go/unicorn/mips_const.go
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Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,10 @@ const (
CPU_MIPS64_I6500 = 9
CPU_MIPS64_LOONGSON_2E = 10
CPU_MIPS64_LOONGSON_2F = 11
CPU_MIPS64_MIPS64DSPR2 = 12
CPU_MIPS64_ENDING = 13
CPU_MIPS64_LOONGSON_3A1000 = 12
CPU_MIPS64_LOONGSON_3A4000 = 13
CPU_MIPS64_MIPS64DSPR2 = 14
CPU_MIPS64_ENDING = 15

// MIPS registers

Expand Down
12 changes: 7 additions & 5 deletions bindings/go/unicorn/riscv_const.go
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Expand Up @@ -5,15 +5,17 @@ const (
// RISCV32 CPU

CPU_RISCV32_ANY = 0
CPU_RISCV32_BASE32 = 1
CPU_RISCV32_SIFIVE_E31 = 2
CPU_RISCV32_SIFIVE_U34 = 3
CPU_RISCV32_ENDING = 4
CPU_RISCV32_BASE = 1
CPU_RISCV32_IBEX = 2
CPU_RISCV32_SIFIVE_E31 = 3
CPU_RISCV32_SIFIVE_E34 = 4
CPU_RISCV32_SIFIVE_U34 = 5
CPU_RISCV32_ENDING = 6

// RISCV64 CPU

CPU_RISCV64_ANY = 0
CPU_RISCV64_BASE64 = 1
CPU_RISCV64_BASE = 1
CPU_RISCV64_SIFIVE_E51 = 2
CPU_RISCV64_SIFIVE_U54 = 3
CPU_RISCV64_ENDING = 4
Expand Down
6 changes: 4 additions & 2 deletions bindings/java/src/main/java/unicorn/MipsConst.java
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Expand Up @@ -38,8 +38,10 @@ public interface MipsConst {
public static final int UC_CPU_MIPS64_I6500 = 9;
public static final int UC_CPU_MIPS64_LOONGSON_2E = 10;
public static final int UC_CPU_MIPS64_LOONGSON_2F = 11;
public static final int UC_CPU_MIPS64_MIPS64DSPR2 = 12;
public static final int UC_CPU_MIPS64_ENDING = 13;
public static final int UC_CPU_MIPS64_LOONGSON_3A1000 = 12;
public static final int UC_CPU_MIPS64_LOONGSON_3A4000 = 13;
public static final int UC_CPU_MIPS64_MIPS64DSPR2 = 14;
public static final int UC_CPU_MIPS64_ENDING = 15;

// MIPS registers

Expand Down
12 changes: 7 additions & 5 deletions bindings/java/src/main/java/unicorn/RiscvConst.java
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Expand Up @@ -7,15 +7,17 @@ public interface RiscvConst {
// RISCV32 CPU

public static final int UC_CPU_RISCV32_ANY = 0;
public static final int UC_CPU_RISCV32_BASE32 = 1;
public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
public static final int UC_CPU_RISCV32_ENDING = 4;
public static final int UC_CPU_RISCV32_BASE = 1;
public static final int UC_CPU_RISCV32_IBEX = 2;
public static final int UC_CPU_RISCV32_SIFIVE_E31 = 3;
public static final int UC_CPU_RISCV32_SIFIVE_E34 = 4;
public static final int UC_CPU_RISCV32_SIFIVE_U34 = 5;
public static final int UC_CPU_RISCV32_ENDING = 6;

// RISCV64 CPU

public static final int UC_CPU_RISCV64_ANY = 0;
public static final int UC_CPU_RISCV64_BASE64 = 1;
public static final int UC_CPU_RISCV64_BASE = 1;
public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;
public static final int UC_CPU_RISCV64_SIFIVE_U54 = 3;
public static final int UC_CPU_RISCV64_ENDING = 4;
Expand Down
8 changes: 5 additions & 3 deletions bindings/pascal/unicorn/MipsConst.pas
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Expand Up @@ -39,8 +39,10 @@ interface
UC_CPU_MIPS64_I6500 = 9;
UC_CPU_MIPS64_LOONGSON_2E = 10;
UC_CPU_MIPS64_LOONGSON_2F = 11;
UC_CPU_MIPS64_MIPS64DSPR2 = 12;
UC_CPU_MIPS64_ENDING = 13;
UC_CPU_MIPS64_LOONGSON_3A1000 = 12;
UC_CPU_MIPS64_LOONGSON_3A4000 = 13;
UC_CPU_MIPS64_MIPS64DSPR2 = 14;
UC_CPU_MIPS64_ENDING = 15;

// MIPS registers

Expand Down Expand Up @@ -242,4 +244,4 @@ interface
UC_MIPS_REG_LO3 = 48;

implementation
end.
end.
14 changes: 8 additions & 6 deletions bindings/pascal/unicorn/RiscvConst.pas
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Expand Up @@ -8,15 +8,17 @@ interface
// RISCV32 CPU

UC_CPU_RISCV32_ANY = 0;
UC_CPU_RISCV32_BASE32 = 1;
UC_CPU_RISCV32_SIFIVE_E31 = 2;
UC_CPU_RISCV32_SIFIVE_U34 = 3;
UC_CPU_RISCV32_ENDING = 4;
UC_CPU_RISCV32_BASE = 1;
UC_CPU_RISCV32_IBEX = 2;
UC_CPU_RISCV32_SIFIVE_E31 = 3;
UC_CPU_RISCV32_SIFIVE_E34 = 4;
UC_CPU_RISCV32_SIFIVE_U34 = 5;
UC_CPU_RISCV32_ENDING = 6;

// RISCV64 CPU

UC_CPU_RISCV64_ANY = 0;
UC_CPU_RISCV64_BASE64 = 1;
UC_CPU_RISCV64_BASE = 1;
UC_CPU_RISCV64_SIFIVE_E51 = 2;
UC_CPU_RISCV64_SIFIVE_U54 = 3;
UC_CPU_RISCV64_ENDING = 4;
Expand Down Expand Up @@ -291,4 +293,4 @@ interface
UC_RISCV_REG_FT11 = 189;

implementation
end.
end.
6 changes: 4 additions & 2 deletions bindings/python/unicorn/mips_const.py
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Original file line number Diff line number Diff line change
Expand Up @@ -34,8 +34,10 @@
UC_CPU_MIPS64_I6500 = 9
UC_CPU_MIPS64_LOONGSON_2E = 10
UC_CPU_MIPS64_LOONGSON_2F = 11
UC_CPU_MIPS64_MIPS64DSPR2 = 12
UC_CPU_MIPS64_ENDING = 13
UC_CPU_MIPS64_LOONGSON_3A1000 = 12
UC_CPU_MIPS64_LOONGSON_3A4000 = 13
UC_CPU_MIPS64_MIPS64DSPR2 = 14
UC_CPU_MIPS64_ENDING = 15

# MIPS registers

Expand Down
12 changes: 7 additions & 5 deletions bindings/python/unicorn/riscv_const.py
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Expand Up @@ -3,15 +3,17 @@
# RISCV32 CPU

UC_CPU_RISCV32_ANY = 0
UC_CPU_RISCV32_BASE32 = 1
UC_CPU_RISCV32_SIFIVE_E31 = 2
UC_CPU_RISCV32_SIFIVE_U34 = 3
UC_CPU_RISCV32_ENDING = 4
UC_CPU_RISCV32_BASE = 1
UC_CPU_RISCV32_IBEX = 2
UC_CPU_RISCV32_SIFIVE_E31 = 3
UC_CPU_RISCV32_SIFIVE_E34 = 4
UC_CPU_RISCV32_SIFIVE_U34 = 5
UC_CPU_RISCV32_ENDING = 6

# RISCV64 CPU

UC_CPU_RISCV64_ANY = 0
UC_CPU_RISCV64_BASE64 = 1
UC_CPU_RISCV64_BASE = 1
UC_CPU_RISCV64_SIFIVE_E51 = 2
UC_CPU_RISCV64_SIFIVE_U54 = 3
UC_CPU_RISCV64_ENDING = 4
Expand Down
6 changes: 4 additions & 2 deletions bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
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Expand Up @@ -36,8 +36,10 @@ module UnicornEngine
UC_CPU_MIPS64_I6500 = 9
UC_CPU_MIPS64_LOONGSON_2E = 10
UC_CPU_MIPS64_LOONGSON_2F = 11
UC_CPU_MIPS64_MIPS64DSPR2 = 12
UC_CPU_MIPS64_ENDING = 13
UC_CPU_MIPS64_LOONGSON_3A1000 = 12
UC_CPU_MIPS64_LOONGSON_3A4000 = 13
UC_CPU_MIPS64_MIPS64DSPR2 = 14
UC_CPU_MIPS64_ENDING = 15

# MIPS registers

Expand Down
12 changes: 7 additions & 5 deletions bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
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Expand Up @@ -5,15 +5,17 @@ module UnicornEngine
# RISCV32 CPU

UC_CPU_RISCV32_ANY = 0
UC_CPU_RISCV32_BASE32 = 1
UC_CPU_RISCV32_SIFIVE_E31 = 2
UC_CPU_RISCV32_SIFIVE_U34 = 3
UC_CPU_RISCV32_ENDING = 4
UC_CPU_RISCV32_BASE = 1
UC_CPU_RISCV32_IBEX = 2
UC_CPU_RISCV32_SIFIVE_E31 = 3
UC_CPU_RISCV32_SIFIVE_E34 = 4
UC_CPU_RISCV32_SIFIVE_U34 = 5
UC_CPU_RISCV32_ENDING = 6

# RISCV64 CPU

UC_CPU_RISCV64_ANY = 0
UC_CPU_RISCV64_BASE64 = 1
UC_CPU_RISCV64_BASE = 1
UC_CPU_RISCV64_SIFIVE_E51 = 2
UC_CPU_RISCV64_SIFIVE_U54 = 3
UC_CPU_RISCV64_ENDING = 4
Expand Down
6 changes: 4 additions & 2 deletions bindings/rust/src/riscv.rs
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Expand Up @@ -349,8 +349,10 @@ impl From<RegisterRISCV> for i32 {
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum Riscv32CpuModel {
UC_CPU_RISCV32_ANY = 0,
UC_CPU_RISCV32_BASE32,
UC_CPU_RISCV32_BASE,
UC_CPU_RISCV32_IBEX,
UC_CPU_RISCV32_SIFIVE_E31,
UC_CPU_RISCV32_SIFIVE_E34,
UC_CPU_RISCV32_SIFIVE_U34,
}

Expand All @@ -370,7 +372,7 @@ impl From<&Riscv32CpuModel> for i32 {
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum Riscv64CpuModel {
UC_CPU_RISCV64_ANY = 0,
UC_CPU_RISCV64_BASE64,
UC_CPU_RISCV64_BASE,
UC_CPU_RISCV64_SIFIVE_E51,
UC_CPU_RISCV64_SIFIVE_U54,
}
Expand Down
6 changes: 4 additions & 2 deletions bindings/zig/unicorn/mips_const.zig
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Expand Up @@ -36,8 +36,10 @@ pub const mipsConst = enum(c_int) {
CPU_MIPS64_I6500 = 9,
CPU_MIPS64_LOONGSON_2E = 10,
CPU_MIPS64_LOONGSON_2F = 11,
CPU_MIPS64_MIPS64DSPR2 = 12,
CPU_MIPS64_ENDING = 13,
CPU_MIPS64_LOONGSON_3A1000 = 12,
CPU_MIPS64_LOONGSON_3A4000 = 13,
CPU_MIPS64_MIPS64DSPR2 = 14,
CPU_MIPS64_ENDING = 15,

// MIPS registers

Expand Down
10 changes: 6 additions & 4 deletions bindings/zig/unicorn/riscv_const.zig
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Expand Up @@ -5,10 +5,12 @@ pub const riscvConst = enum(c_int) {
// RISCV32 CPU

CPU_RISCV32_ANY = 0,
CPU_RISCV32_BASE32 = 1,
CPU_RISCV32_SIFIVE_E31 = 2,
CPU_RISCV32_SIFIVE_U34 = 3,
CPU_RISCV32_ENDING = 4,
CPU_RISCV32_BASE = 1,
CPU_RISCV32_IBEX = 2,
CPU_RISCV32_SIFIVE_E31 = 3,
CPU_RISCV32_SIFIVE_E34 = 4,
CPU_RISCV32_SIFIVE_U34 = 5,
CPU_RISCV32_ENDING = 6,

// RISCV64 CPU

Expand Down
2 changes: 2 additions & 0 deletions include/unicorn/mips.h
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Expand Up @@ -55,6 +55,8 @@ typedef enum uc_cpu_mips64 {
UC_CPU_MIPS64_I6500,
UC_CPU_MIPS64_LOONGSON_2E,
UC_CPU_MIPS64_LOONGSON_2F,
UC_CPU_MIPS64_LOONGSON_3A1000,
UC_CPU_MIPS64_LOONGSON_3A4000,
UC_CPU_MIPS64_MIPS64DSPR2,

UC_CPU_MIPS64_ENDING
Expand Down
6 changes: 4 additions & 2 deletions include/unicorn/riscv.h
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Expand Up @@ -18,8 +18,10 @@ extern "C" {
//> RISCV32 CPU
typedef enum uc_cpu_riscv32 {
UC_CPU_RISCV32_ANY = 0,
UC_CPU_RISCV32_BASE32,
UC_CPU_RISCV32_BASE,
UC_CPU_RISCV32_IBEX,
UC_CPU_RISCV32_SIFIVE_E31,
UC_CPU_RISCV32_SIFIVE_E34,
UC_CPU_RISCV32_SIFIVE_U34,

UC_CPU_RISCV32_ENDING
Expand All @@ -28,7 +30,7 @@ typedef enum uc_cpu_riscv32 {
//> RISCV64 CPU
typedef enum uc_cpu_riscv64 {
UC_CPU_RISCV64_ANY = 0,
UC_CPU_RISCV64_BASE64,
UC_CPU_RISCV64_BASE,
UC_CPU_RISCV64_SIFIVE_E51,
UC_CPU_RISCV64_SIFIVE_U54,

Expand Down
12 changes: 12 additions & 0 deletions include/unicorn/unicorn.h
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Expand Up @@ -69,6 +69,18 @@ typedef size_t uc_hook;
#define UNICORN_DEPRECATED
#endif

#ifdef _MSC_VER
#define UNICORN_UNUSED __pragma(warning(suppress : 4101))
#else
#define UNICORN_UNUSED __attribute__((unused))
#endif

#ifdef _MSC_VER
#define UNICORN_NONNULL
#else
#define UNICORN_NONNULL __attribute__((nonnull))
#endif

// Unicorn API version
#define UC_API_MAJOR 2
#define UC_API_MINOR 1
Expand Down
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