Creating Semiconductor Engineering Training Programs

“Education of Chip Designers at a Large Scale: A Proposal” – Prof. Behzad Razavi (IEEE SSC Magazine, Spring 2024) In this article, Prof. Razavi shares his experience about an industry-oriented training course on chip design, which is also called “Tapeout Class.”   The article starts with a very relevant question: “Most of the CHIPS Act fund goes to chip fabrication. Who will design the chips that must fill the capacity of these fabrication lines?” Indeed, governments are showing unprecedented interests in semiconductor fabrication facilities in order to build robust domestic supply chain. In this process, chip (circuit) design skill remains out of focus. An industry-oriented chip design course can address this issue and strongly help produce a significant number of future talents for industry.   In this article, Prof. Razavi describes his experience and the issues he faced during the chip design course in a very lively manner. Young people, willing to develop a career in chip design, would surely benefit from this article because it explains the steps in the chip design process quite authentically with a reasonable timeline. Overall, the idea of the chip design course or “tapeout class” sounds great.       Prof. Razavi concludes the article with some truly practical remarks. “The instructor does need to have an in-depth knowledge of the project topics as well as extensive experience in chip design and measurement. If left to their own devices, even highly intelligent students may develop faulty chips, thereby resenting their experience.” In this regard, I consider myself fortunate enough to have worked with some of the great circuit designers in industry and academia. Link to the article: https://lnkd.in/ekPnE-N3 #chip_design #ic_design #circuit_design

🇮🇳 5 Ways Fabs & OSATs Will Build India’s Semiconductor Ecosystem ✅ 1) Create Anchor Demand → Pull the Supply Chain Into India Once fabs and OSATs commit billions, suppliers follow automatically — gases, chemicals, CMP pads, wet benches, wafers, bonding wire, leadframes, packaging substrates, tools, spare parts. India examples • Micron ATMP (Sanand) → pulling in chemicals, automation vendors, cleanroom firms • Tata OSAT (Dholera) → attracting bonding wire, molding compounds, test equipment service providers • Tata Semiconductor Fab (Dholera) → supply chain planning for gases, CMP slurries, UPW, STP, photochemicals Effect: India shifts from importing fab inputs to manufacturing + supplying them. ✅ 2) Build Semiconductor Talent Pipelines Fabs and ATMP plants don’t just hire — they restructure university pipelines and vocational training. How it plays out • Cleanroom operator programs • Semiconductor technician diplomas (ITI/Polytechnic) • Fab engineer specializations in IITs/NITs Examples • Dholera + IIT partnerships for fab-ready curriculum • PDPU + ISM + Techovedas cleanroom skilling ecosystem • Karnataka semiconductor skill cluster (DRDO + CDAC + private fabs) Effect: A fab-ready workforce — technicians, EHS, yield, metrology, automation engineers. ✅ 3) Technology & Process Transfer Into India Real capability grows when we internalize process know-how and yield learning. Examples • PSMC tech transfer for 28nm with Tata • Micron’s global ATMP playbook → imported to Gujarat • Gallium Nitride pilot lines in IISc + IIT campuses with industry tie-ups Effect: India learns process IP, yield engineering, reliability + automotive grade quality systems. ✅ 4) Catalyze Fabless + Hardware & EMS Growth Packaging & test proximity reduces cycle time & logistics cost → fuels design + electronics industries. Examples • Saankhya Labs, Signalchip, Morphing Machines — benefit from local test ecosystem • VVDN, Kaynes → link design → prototyping → PCBA → test • Micron + Tata OSAT → expected to serve defence, telecom, automotive fabless firms Effect: India moves from PCB assembly → chip design → packaging → systems manufacturing. ✅ 5) Trigger Industrial Policy Flywheel Fabs force the government to solve the right problems: What gets built • Logistics corridors • Power redundancy + clean power • Specialty gas networks • Waste recycling + UPW plants • Custom bonded warehousing Current progress • Gujarat Semiconductor Mission (Dholera-Sanand corridor) • Karnataka and TN building packaging + design clusters • Haryana, Maharashtra pushing “electronics valley” incentives Effect: Semiconductor policy → becomes industrial transformation policy. ~~~~~~ If you are looking to invest in semiconductors and need expert insights, drop us a DM.

Shortage of Analog Circuit Designers: A Brief Overview The Problem: In recent years, the electronics industry has faced a growing shortage of skilled analog circuit designers. Unlike digital design, which benefits from extensive automation tools, analog design remains a highly specialized, manual, and experience-driven field. The demand for analog circuits — especially in areas like power management, RF, sensors, and mixed-signal ICs — continues to rise, but the supply of qualified engineers is not keeping pace. Key Reasons for the Shortage: 1. Steep Learning Curve: Analog design requires deep understanding of circuit behavior, noise, parasitics, and process variations — skills that take years to master. 2. Fewer Educational Opportunities: University curricula often focus more on digital design, with limited practical exposure to analog systems. 3. Lack of Mentorship: As experienced analog designers retire, there are fewer mentors to train the next generation. 4. Limited Design Automation: Analog design can’t be fully automated like digital, making it less appealing to new engineers. 5. Industry Shift Toward Software: Many students are drawn toward software, AI, or digital VLSI fields that appear more dynamic and offer faster career growth. ⸻ What Can Be Done? 1. Academic Revamp • Introduce and emphasize analog circuit design in undergraduate and graduate courses. • Provide hands-on labs and real-world design challenges to make analog more engaging. 2. Industry-Academia Collaboration • Companies can sponsor analog-focused programs, internships, and design contests. • Provide accessible simulation tools (e.g., simplified SPICE environments) for students. 3. Upskilling & Mentorship • Senior designers should be encouraged and incentivized to mentor junior engineers. • Establish structured analog design training programs within companies. 4. Promoting Analog Careers • Highlight the impact and innovation of analog roles (e.g., in biomedical, aerospace, and IoT). • Offer competitive salaries and career paths to retain analog talent. 5. Tool Development • Invest in semi-automated analog design tools to reduce design time and effort. ⸻ Conclusion: The analog design talent gap is a pressing challenge in the semiconductor industry. Bridging it will require coordinated efforts across academia, industry, and the engineering community. By making analog design more accessible, supported, and rewarding, we can ensure a strong future for this essential domain of electronics.

From RTL to Reusable Methodologies: Students advancing through UVM, Automation and Physical Aware Design. As we are wrap up the term, students are progressing through a powerful learning curve. In my Functional Verification cohort, they begin with traditional Verilog testbenches, then migrate to SystemVerilog class-based environments and ultimately culminate in full UVM-based verification framworks. They are applying these methodologies to industry-relevant designs such as: + Multi-processor systems with memory controllers + DDR5 - PHY interfaces + Asynchronous FIFO + AXI-4 protocol verification + MIPS CPU implementations + AHB-to-APB bridge verifications They have transitioned from directed stimulus to constrained-random verification, reusable components, scoreboards and coverage-driven verification while building scalable and reusable verification environments. Meanwhile the Synthesis and Modeling cohort is diving into explorative analysis, automation and building solid foundation for the Physical Design of Integrated Circuits. + Integer multiplier optimization using TCL automation + Multi-VT analysis and trade-off exploration + Multi-frequency sweep QoR automation + Automated Multi-VT analysis of RISC-V core with DFT considerations + Top-down vs Bottom-Up Synthesis analysis + Achieving maximum attainable frequency through iterative timing closure strategies Goal here is to develop engineers who can think architecturally, automate intelligently and validate rigorously. Proud to see students applying knowledge into structured methodology, automation thinking and real-world semiconductor workflows.

  New-generation Faculty Leaders Aim to Transform Indian Design, Semiconductor, Packaging, and Systems (IDSPS) with Next-Gen R&D and Workforce Initiative. The three-way partnership between Meity, academia, and industry created IDSPS as a national R&D and workforce program with 80 faculty from 30 Institutions and 80 global companies. Together, they made outstanding progress. They are ready to form industry consortiums in 12 industry centers to build the nation, educate 2000 Ph. Ds, 3000 MTech, 3000 BTech, and reeducate 15,000 industry engineers, as described below. 1. System Designs and Architectures by Profs. Kumar (IITJ) & Sharma (IIT Ropar) focuses on high-bandwidth computing, power efficiency, privacy, and security, as well as design for signal, power, EMI, and ESD. 2. CMOS Devices by Profs. Mohapatra (IITGN) & Dixit (IITD) focuses on the next-gen (< 3nm) semiconductor materials, process modeling, and characterization of logic and memory devices. Power Devices by Profs. Akshay K (IIT BBS) & Brag (IITG) focuses on device modeling, simulation and design, substrate and epi growth, device fabrication and characterization.  3. Package Substrates by Profs. Dixit (IITB) &Arora (IITJ) focuses on glass substrates with advances in package design, embedded components, large panel lithography, and polymer-Cu RDL  4. Co-packaged Optics by Profs. Emani (IITH) & Sudharsanan (ITTM) focuses on design of co-packaged optics for higher bandwidth at lower power than electronic packages, photonic interconnections, hybrid bonding assembly, and fiber coupling.  5. Predictive Modeling & Design by Profs. Agarwal (IITGN)& Roy (IITKGP) focuses on AI- assisted design for reliability, multi-physics design, materials, interfaces and stress development.  6. 6G Integrated Systems by Profs. Mandal (IITKGP), Duttagupta (IITB)& Kumar (IITG) focuses on low-loss glass substrates with embedded devices, components, and package-integrated antennas.  7. Integrated Sensors & MEMS by Profs. Mitra (IITD)& KP Rao (BITS) focus on new concepts in inertial sensors, resonators, printed sensors,2D materials, and sensor fusion.  8 Materials for Devices, Components & Packaging by Profs. Bhagwati on non-volatile memory, Kumar(IISc) on package materials & Murali (NIT Calicut) on components.  9. IC and Board Assembly by Profs. Badwe (IITK) & Govind Singh (IITH) focuses on Cu-Cu bonding, sintered Cu die-attach and fiber coupling assembly.  10. Thermal Technologies by Profs. Bhattacharya(IITKGP) &Ambirajan(IISc) focuses on liquid cold plates, 2-phase and boiling heat transfer, and thermal interfaces.  11. Integrated Power Electronics by Profs. Shiladri(ITB) & Yadav(IITR) focuses on integrated power modules with advances in system design, power devices, components, sintered-Cu die attach, and double-side liquid cooling.   12. System Electrical Test by Profs. Tudu (IIT TP) & Ahlawat (IIT Jammu) focuses on test advances in chiplets, 2.5D glass packages, boundary scan, analog and mixed signal.