Silicon Photonics Technology Advancements

Using light as a neural network, as this viral video depicts, is actually closer than you think. In 5-10yrs, we could have matrix multiplications in constant time O(1) with 95% less energy. This is the next era of Moore's Law. Let's talk about Silicon Photonics... The core concept: Replace electrical signals with photons. While current processors push electrons through metal pathways, photonic systems use light beams, operating at fundamentally higher speeds (electronic signals in copper are 3x slower) with minimal heat generation. It's way faster. While traditional chips operate at 3-5 GHz, photonic devices can achieve >100 GHz switching speeds. Current interconnects max out at ~100 Gb/s. Photonic links have demonstrated 2+ Tb/s on a single channel. A single optical path can carry 64+ signals. It's way more energy efficient. Current chip-to-chip communication costs ~1-10pJ/bit. Photonic interconnects demonstrate 0.01-0.1pJ/bit. For data centers processing exabytes, this 200x improvement means the difference between megawatt and kilowatt power requirements. The AI acceleration potential is revolutionary. Matrix operations, fundamental to deep learning, become near-instantaneous: Traditional chips: O(n²) operations. Photonic chips: O(1) - parallel processing through optical interference. 1000×1000 matmuls in picoseconds. Where are we today? Real products are shipping: — Intel's 400G transceivers use silicon photonics. — Ayar Labs demonstrates 2Tb/s chip-to-chip links with AMD EPYC processors. Performance scales with wavelength count, not just frequency like traditional electronics. The manufacturing challenges are immense. — Current yield is ~30%. Silicon's terrible at emitting light and bonding III-V materials to it lowers yield — Temp control is a barrier. A 1°C change shifts frequencies by ~10GHz. — Cost/device is $1000s To reach mass production we need: 90%+ yield rates, sub-$100 per device costs, automated testing solutions, and reliable packaging techniques. Current packaging alone can cost more than the chip itself. We're 5+ years from hitting these targets. Companies to watch: ASML (manufacturing), Intel (data center), Lightmatter (AI), Ayar Labs (chip interconnects). The technology requires major investment, but the potential returns are enormous as we hit traditional electronics' physical limits.

The way we move data inside our chips is hitting a limit… Moving data with electrons is simply too heavy for the next generation of computing. Every time we push electricity through metal wires it creates friction. If we try to make chips move data any faster the resistance creates enough heat to melt the silicon. This is why AI power consumption is spiraling. Lightmatter found the solution…. Their platform called Passage replaces copper wires with Silicon Photonics. Instead of electricity it uses beams of light moving through microscopic glass tunnels. • Zero Mass: Photons move with no resistance and virtually no heat. • 100x Faster: Their M1000 chip moves 114 Terabits of data per second. This dwarfs traditional electronic interconnects. • Green AI: We can finally scale AI models to be 1000x smarter without overloading the global power grid. The future of computing is not just about smaller transistors. It is about moving at the speed of light!! 📚 Resources and Learn More • Lightmatter Official Press: “Lightmatter Unveils Passage M1000 Photonic Superchip” (March 2025). • Hot Chips 2025 Presentation: Darius Bunandar, “Passage M1000: 3D Photonic Interposer for AI.” • Lightmatter Technical Blog: “Seeing is Believing: A Technical Deep Dive into Lightmatter Hardware” (September 2025). • HPCwire Analysis: “Lightmatter Aims to Leapfrog I/O Limitations with 3D Photonic Interconnect” (December 2025). #techexplained #futuretech #ai

Silicon Photonics in 2026: The Shift From Trend to Transition LightCounting’s forecast—over 50% of optical transceiver sales using silicon-photonics modulators in 2026 up from 10% in 2018—represents a dramatic industry inflection. This shift is being driven by four major forces: ✅ 1. Explosive Bandwidth Demand from AI Clusters AI workloads (ChatGPT-class models, large-scale training clusters, hyperscale inference) require: • 800G → 1.6T optical transceivers • low power / low-latency interconnects • tight integration between compute and optics Electrical interconnects saturate around a few centimeters at >100 Gbps. Silicon photonics eliminates these physical limits, enabling co-packaged optics and eventually optical I/O directly integrated with advanced packaging. ✅ 2. Foundries Reconfiguring Their Roadmaps for SiPh The foundry landscape is shifting from small experimental lines to full commercial 300 mm manufacturing. The table you shared captures this transformation. ✅ 3. Wafer Transition: 200 mm → 300 mm This is one of the biggest structural shifts. Why 300 mm matters: • Better uniformity of waveguides and modulators • Higher yield for photonic components • Economies of scale similar to CMOS • Better compatibility with advanced packaging As transceiver volumes scale with AI datacenters, 200 mm lines (like Tower’s current base) cannot meet hyperscale demand. Most commercial deployment in 2026+ will rely on 300 mm. ✅ 4. Packaging Becomes the Real Battlefield Silicon photonics != complete system The real bottleneck is packaging and fiber alignment. Three major approaches are emerging: 1. Co-Packaged Optics (CPO) Optical engines integrated beside switch ASICs. TSMC and Nvidia are pushing this. 2. Pluggable Transceivers Using SiPh Still dominant today (800G / 1.6T). GF and Intel lead here. 3. Optical I/O / Optical Chiplets Future vision — optical communication directly connected to compute tiles. This requires: • ultra-low-loss coupling • integrated lasers or hybrid bonding • photonic + electronic co-design Expect early pilot deployments around 2027–2028.

🔴 Researchers from imec, EPFL, KTH Royal Institute of Technology, and Tyndall National Institute present the blueprint for next-generation integrated photonics in #MicrosystemsAndNanoengineering. The paper "Integrated silicon photonic MEMS" proves that combining micro electromechanical systems with standard foundry processes will define the next decade of #SiliconPhotonics and #OpticalComputing. While silicon photonics has emerged as a mature technology for high data rate communications and autonomous vehicle sensing, the material's weak electro-optic effects remain a bottleneck. Traditional thermo-optic tuning devices demand continuous power consumption and result in large footprints. This comprehensive research proves that integrating MEMS directly into silicon photonic circuits is the ultimate solution. 1️⃣ Overcoming Material Limits: #PhotonicMEMS & #EnergyEfficiency By replacing bulky traditional modulators with silicon photonic MEMS, the architecture drastically reduces the device footprint. Furthermore, it introduces bistable phase switches that enable nonvolatile photonic circuits, eliminating the need for continuous static power consumption. 2️⃣ Wafer Level Scalability: #Foundry & #Packaging The true breakthrough lies in manufacturability. The research highlights the successful implementation of wafer-level hermetically sealed packaging. This ensures that these advanced MEMS components can be produced with high yield and high volume capacity using standardized silicon foundries. 3️⃣ Reconfigurable Architectures: #OpticalRouting & #QuantumInformation This scalable integration provides access to fully reconfigurable coupled resonator optical waveguides. It unlocks optimized library components for complex optical routing, paving the way for advanced photonic accelerated computing and quantum information processing. 💡 My Take: As the demands of AI and data centers push optical communication to its limits, the massive power consumption of thermo-optic tuning in traditional silicon photonics is no longer sustainable. By physically moving microscopic silicon structures using MEMS, we can route light with near-zero static power. This research is a massive wake-up call for the industry. Transitioning from solid-state thermal tuning to wafer-scale integrated photonic MEMS is not just an incremental hardware update, it is a mandatory architectural revolution required to build energy-efficient, large-scale optical networks. 👇 Link in the comments #AdvancedPackaging #HardwareArchitecture #Metrology #3DIC #DataCenter #AIHardware #Telecommunications #Optoelectronics Intel TSMC Samsung Electronics GlobalFoundries NVIDIA Broadcom Marvell Technology Cisco Applied Materials ASML Lam Research Lumentum Coherent Corp. Infinera STMicroelectronics

In the October 2025 Issue of IEEE Journal of Solid-State Circuits (JSSC) 🏷️https://lnkd.in/ggycZQHn, researchers from Chinese Academy of Sciences reported a monolithic dense wavelength-division multiplexing (#DWDM) silicon-photonics (#SiPh) transceiver. Fabricated in a 45nm silicon-on-insulator (#SOI) CMOS process and operating at 50Gbps/λ lane speed, the transceiver achieves 176Gbps/mm2 bandwidth density and 3.5pJ/bit power efficiency, which can be enhanced to 224Gbps/mm2 and 2.85pJ/bit at 64Gbps/λ or equivalently, 256Gbps/fiber with 4 lanes/fiber. Excerpts (edited): 📝This work proposes a transceiver built on an electronic-photonic integrated chip (#EPIC) and reports these innovations: 1) co-designing optical resonators with electrical equalizers (EQ) to achieve a 200GHz wavelength (λ) spacing at 50Gbps/λ; 2) applying asymmetric inductive-peaking equalization to compensate for the micro-ring modulator (#MRM)’s insufficient bandwidth (BW) and high nonlinearity; 3) co-designing the transimpedance amplifier (#TIA) with EQs to mitigate the BW limitation imposed by high-Q micro-ring filters (#MRF). 📝In the TX, 4 drivers control 4 cascaded MRMs, each tuned to a different wavelength. Each MRM is driven differentially at its anode and cathode through ac-coupling capacitors. 📝In the RX, 4 MRFs are applied to select light at their respective TX wavelengths. This generates a narrowband/bandpass spectral response at each drop port, allowing the MRF to execute wavelength-selective filtering and mitigate interference from adjacent channels. 📝The total #transceiver die area is 3.5x2.2mm2. TX and RX active areas (per channel) are 0.33 and 0.24mm2, respectively. A six-core fiber array (FA) is vertically coupled to the optical interface between TX (left) and RX (right) as depicted below. 🔍Observations: Though both MRM and MRF are based on optical resonance, which occurs when the optical path length of a resonator—made of either silicon or polymer—is an integer multiple of a given wavelength, leading to buildup of light intensity at that wavelength, the former is an active device and the latter passive: MRM alters/tunes the input signal's optical/electrical properties and warrants energy intake, while MRF optically blocks/drops a given wavelength, without the need for electrical (voltage or current) control. Table I offers an informative comparison of multiple monolithic and 3D-stacking ("hybrid-3D") implementations of “EIC+PIC” combos, despite a minor mix-up in bibliography, which #AI didn't catch. As demonstrated in #CPO Example (V), on-chip lasers are hard but possible. Further reading: 🏷️Full article: https://lnkd.in/gBb8eHqA 🏷️CPO Example (V): https://lnkd.in/gAGh_nwK 🏷️CPO Example (X): https://lnkd.in/gNXPSDBW 🏷️CPO Example (XI): https://lnkd.in/gtne7VbB 🏷️CPO Options: https://lnkd.in/g9v53iXM 🏷️MRM or EAM: https://lnkd.in/guqkqhGZ ➟ To be continued. #SemiconductorIndustry #Semiconductor #Semiconductors #OIO #OCI #JustChips 

MIT Unveils AI Chip That Operates Entirely on Light, Not Electricity Researchers at MIT have created a revolutionary AI accelerator chip that performs computations entirely using light rather than electricity potentially slashing energy consumption in data centers by over 90%. This photonic AI chip leverages arrays of nano-optic waveguides and micro-ring modulators to process data using beams of modulated light. At its core, the chip replaces electrical transistors with tiny optical interference units that manipulate light’s phase and amplitude. Matrix multiplications, the backbone of neural networks, are executed as light passes through a mesh of these units, eliminating resistive heating entirely. The chip has no moving parts and transmits information at the speed of light, literally. Initial tests showed the photonic processor performing convolutional neural network (CNN) tasks at 10 teraflops per watt far surpassing Nvidia’s top-tier GPUs. What’s more, it generates no heat beyond the laser source itself, drastically simplifying cooling and thermal design. MIT’s prototype uses silicon photonics and is fully compatible with existing CMOS processes, making it scalable for commercial production. Future versions may be paired with on-chip photonic memory, enabling entirely light-driven inference systems. The team envisions hyperscale data centers running vast language models on these chips with almost no electricity use, ushering in a post-electronic computing era. Note: The opinions expressed here are solely my own and do not represent my employer.

📈 Silicon built the web. Light will scale the AI factory.
 The acceleration of the data‑center economy is now visibly reshaping major stock indices. Yesterday, Vertiv, Lumentum, and Coherent Corp. were announced as new entrants to the S&P 500, adding close to $210B in combined market capitalization — including EchoStar — on a day when the index itself rose by about $150B. This marks a new turning point. 🔬Photonics moves to the center of the AI factory
Just days earlier, NVIDIA announced a $2B investment in Coherent, alongside another $2B in Lumentum — a combined $4B bet on silicon photonics as the backbone of next‑generation AI data centers. 
These partnerships include multi‑billion‑dollar purchase commitments and future capacity rights, confirming one thing: light‑based interconnects are becoming the critical bottleneck‑breaker for AI scale‑up. Early estimates suggest 7–10% reductions in energy and water usage, as photonics‑based interconnects meaningfully cut electrical losses and cooling requirements. These gains translate directly into higher efficiency and lower opex for hyperscale operators. This is not just a move away from copper‑based bottlenecks — copper simply cannot support trillion‑parameter models at scale. Instead, it signals the beginning of a structural shift: from the silicon economy to the silicon‑photonics economy, where profitability grows not through higher capex, but because the same capex delivers far more performance per watt. And it highlights the vitality of the U.S. innovation ecosystem, even in manufacturing. Lumentum and Vertiv were founded less than a decade ago...
It’s not just California. Vertiv is headquartered in Ohio; Coherent in Pennsylvania. #AgeOfHypertransformation

TSMC + Avicena: Reinventing Optical Interconnects Without Lasers As AI and HPC workloads explode, power-hungry copper links and complex laser-based optics are hitting their limits. Enter a game-changing collaboration: TSMC and Avicena are developing a MicroLED-based optical interconnect — no lasers, no modulators, just ultra-efficient light powered by CMOS integrated MicroLEDs. ▫️ Sub-pJ/bit energy efficiency ▫️ Simplified design using LED arrays instead of high-speed modulators ▫️ Short-to-medium reach (10–30m+), ideal for intra-rack AI GPU links ▫️ TSMC brings chiplet and CMOS image-sensor expertise to scale production ▫️ CPO vs. MicroLED LightBundle - CPO (Co-Packaged Optics): Relies on lasers, high-speed modulators, and fiber coupling, adding complexity, thermal constraints, and cost. - LightBundle (MicroLED): Uses direct-emitting MicroLEDs and imaging fibers — simpler, lower power (<1 pJ/bit), and easier to scale on-chip. Compared to CPO, the LightBundle solution can dramatically reduce system complexity, energy consumption, and cost, making it a strong candidate for next-gen AI infrastructure. 💡 This may not just be another interconnect, it’s a new class of optical I/O. It’s really worth watching. Reference source: [Avicena Press Release](https://lnkd.in/gqCkGUgq) Learn more: [IEEE Spectrum – TSMC’s MicroLED Optical Leap](https://lnkd.in/gVKpmP2a) #TSMC #Avicena #MicroLED #SiliconPhotonics #CPO #OpticalInterconnect #AIInfrastructure #Semiconductors #DataCenter #Chiplet #Photonics #TechInnovation #TSMCTech #AIHPC #CMOS #NextGenNetworking

💡🚀 Ge-on-Si Photodiodes: How Do Photonic Chips Detect Light? 🚀💡 Photonic chips can guide, split, modulate, and filter light. But eventually, they must convert optical signals back into electrical ones. That’s the job of a photodiode. In silicon photonics, one of the most important solutions is the Germanium-on-Silicon (Ge-on-Si) photodiode. ✨ Why not silicon alone? ✨ At telecom wavelengths (1310 nm and 1550 nm), silicon absorbs light very poorly because of its indirect band gap. In direct band gap materials, electrons can absorb or emit photons efficiently. In indirect band gap materials like silicon, a phonon is also required to conserve momentum, making optical absorption much weaker. Germanium, however, absorbs telecom light much more efficiently, making it ideal for photodetection. That combination is powerful: ✅ Silicon provides the photonic platform ✅ Germanium provides efficient light absorption ✨ How does a Ge-on-Si photodiode work? ✨ A typical device includes: 🔹 A silicon waveguide 🔹 A germanium absorption region 🔹 A pn or pin junction 🔹 Metal contacts for readout As light travels through the waveguide: ➡️ Light is absorbed in germanium ➡️ Electron-hole pairs are generated ➡️ An electrical current is produced This is the photoelectric effect in action. ✨ Why is germanium widely used? ✨ Because it offers: ✅ Strong telecom-wavelength absorption ✅ CMOS-compatible integration ✅ High-speed operation ✅ Compact device footprint ✨ Key performance metrics ✨ Photodiodes are evaluated by: 🔹 Responsivity 🔹 Bandwidth 🔹 Dark current 🔹 Noise performance And like many photonic devices, there are trade-offs: 📈 More absorption improves efficiency 📉 But can reduce speed So designers must balance: ⚡ Speed 💡 Efficiency 🔌 Electrical performance ✨ Why are Ge-on-Si photodiodes important? ✨ They are essential for: 🔹 Optical communication receivers 🔹 Datacenter interconnects 🔹 LiDAR 🔹 Optical sensing 🔹 High-speed transceivers They form the bridge between: 💡 Photonics and 🔌 Electronics So here’s a question for you 👇 Do you know of any other materials that can be used to detect light in silicon photonics? #SiliconPhotonics #Photonics #Photodiode #Germanium #IntegratedPhotonics #TechExplained #LearnPhotonics

𝗙𝗿𝗼𝗺 𝗕𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸 𝘁𝗼 𝗕𝗿𝗲𝗮𝗸𝘁𝗵𝗿𝗼𝘂𝗴𝗵: 𝗛𝗼𝘄 𝗣𝗵𝗼𝘁𝗼𝗻𝗶𝗰𝘀 𝗜𝗻𝘁𝗲𝗿𝗰𝗼𝗻𝗻𝗲𝗰𝘁𝘀 𝗮𝗿𝗲 𝗥𝗲𝘄𝗶𝗿𝗶𝗻𝗴 𝘁𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 𝗼𝗳 𝗔𝗜 & 𝗗𝗮𝘁𝗮 𝗖𝗲𝗻𝘁𝗲𝗿𝘀 The future of AI and high-performance computing won’t be defined by silicon alone. 𝗔𝘀 𝗺𝗼𝗱𝗲𝗹𝘀 𝘀𝗰𝗮𝗹𝗲, 𝗺𝗼𝘃𝗶𝗻𝗴 𝗱𝗮𝘁𝗮—𝗻𝗼𝘁 𝗷𝘂𝘀𝘁 𝗰𝗼𝗺𝗽𝘂𝘁𝗶𝗻𝗴—𝗵𝗮𝘀 𝗯𝗲𝗰𝗼𝗺𝗲 𝘁𝗵𝗲 𝗿𝗲𝗮𝗹 𝗯𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸 𝗳𝗼𝗿 𝗮𝗰𝗰𝗲𝗹𝗲𝗿𝗮𝘁𝗼𝗿𝘀. The limits of copper wires are now holding back bandwidth, power efficiency, and ultimately, AI’s progress. 𝗖𝘂𝗿𝗿𝗲𝗻𝘁 𝗖𝗵𝗮𝗹𝗹𝗲𝗻𝗴𝗲𝘀  • 𝗘𝘀𝗰𝗮𝗹𝗮𝘁𝗶𝗻𝗴 𝗽𝗼𝘄𝗲𝗿 𝘂𝘀𝗮𝗴𝗲: High-speed electrical I/O burns enormous power, especially as bandwidth demands rise.  • 𝗕𝗮𝗻𝗱𝘄𝗶𝗱𝘁𝗵 𝗯𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸𝘀: Copper wires face a ceiling for how much data they can carry, with signal degradation and crosstalk worsening at higher speeds.  • 𝗟𝗮𝘁𝗲𝗻𝗰𝘆 & 𝘀𝗰𝗮𝗹𝗶𝗻𝗴: Traditional interconnects add latency, and scaling to larger multi-chip or multi-rack systems often requires even more energy and complex routing. 𝗣𝗵𝗼𝘁𝗼𝗻𝗶𝗰𝘀: 𝗧𝗵𝗲 𝗦𝗼𝗹𝘂𝘁𝗶𝗼𝗻 #Photonics - using light instead of electricity to move data—offers a path to break through these barriers:  • 𝗨𝗹𝘁𝗿𝗮-𝗵𝗶𝗴𝗵 𝗯𝗮𝗻𝗱𝘄𝗶𝗱𝘁𝗵: Photonic links deliver terabits per second between chips, boards, and racks.  • 𝗟𝗼𝘄𝗲𝗿 𝗽𝗼𝘄𝗲𝗿 𝗽𝗲𝗿 𝗯𝗶𝘁: Photonics reduces wasted energy as heat, enabling higher density and sustainability.  • 𝗟𝗼𝗻𝗴𝗲𝗿 𝗿𝗲𝗮𝗰𝗵, 𝗹𝗼𝘄𝗲𝗿 𝗹𝗮𝘁𝗲𝗻𝗰𝘆: Optical signals maintain integrity over longer distances, crucial for modular and disaggregated architectures. 𝗞𝗲𝘆 𝗛𝘂𝗿𝗱𝗹𝗲𝘀 𝗳𝗼𝗿 𝗠𝗮𝗶𝗻𝘀𝘁𝗿𝗲𝗮𝗺 𝗔𝗱𝗼𝗽𝘁𝗶𝗼𝗻  • 𝗖𝗠𝗢𝗦 𝗶𝗻𝘁𝗲𝗴𝗿𝗮𝘁𝗶𝗼𝗻: Integrating lasers, modulators, and photodetectors with silicon is still complex.  • 𝗣𝗮𝗰𝗸𝗮𝗴𝗶𝗻𝗴 & 𝘆𝗶𝗲𝗹𝗱: High-precision assembly is required; small misalignments can hurt performance and scale-up.  • 𝗧𝗵𝗲𝗿𝗺𝗮𝗹 𝗺𝗮𝗻𝗮𝗴𝗲𝗺𝗲𝗻𝘁: On-chip lasers and drivers add new thermal challenges.  • 𝗖𝗼𝘀𝘁 & 𝗲𝗰𝗼𝘀𝘆𝘀𝘁𝗲𝗺: Photonic components are costlier so volume manufacturing and mature standards are just emerging.  • 𝗦𝗼𝗳𝘁𝘄𝗮𝗿𝗲/𝗮𝗿𝗰𝗵𝗶𝘁𝗲𝗰𝘁𝘂𝗿𝗲: Fully exploiting photonics requires new networking stacks, protocols, and sometimes rethinking system design. 𝗣𝗵𝗼𝘁𝗼𝗻𝗶𝗰𝘀 𝗶𝘀 𝗻𝗼 𝗹𝗼𝗻𝗴𝗲𝗿 𝗷𝘂𝘀𝘁 𝗮 𝗿𝗲𝘀𝗲𝗮𝗿𝗰𝗵 𝘁𝗼𝗽𝗶𝗰—𝗶𝘁’𝘀 𝗻𝗼𝘄 𝘂𝗻𝗹𝗼𝗰𝗸𝗶𝗻𝗴 𝗻𝗲𝘄 𝗳𝗿𝗼𝗻𝘁𝗶𝗲𝗿𝘀 𝗶𝗻 𝗽𝗲𝗿𝗳𝗼𝗿𝗺𝗮𝗻𝗰𝗲 𝗮𝗻𝗱 𝗲𝗳𝗳𝗶𝗰𝗶𝗲𝗻𝗰𝘆 𝗳𝗼𝗿 #𝗔𝗜 𝗮𝗻𝗱 𝗰𝗹𝗼𝘂𝗱 #𝗰𝗼𝗺𝗽𝘂𝘁𝗶𝗻𝗴. The transition from electrons to photons is happening, but its tipping point will depend on integration, ecosystem, and system design breakthroughs. 𝗪𝗵𝗲𝗿𝗲 𝗱𝗼 𝘆𝗼𝘂 𝘀𝗲𝗲 𝘁𝗵𝗲 𝗯𝗶𝗴𝗴𝗲𝘀𝘁 𝗵𝘂𝗿𝗱𝗹𝗲𝘀—𝗼𝗿 𝗼𝗽𝗽𝗼𝗿𝘁𝘂𝗻𝗶𝘁𝗶𝗲𝘀—𝗳𝗼𝗿 𝗽𝗵𝗼𝘁𝗼𝗻𝗶𝗰𝘀 𝗶𝗻 𝗿𝗲𝘀𝗵𝗮𝗽𝗶𝗻𝗴 𝗱𝗮𝘁𝗮 𝗺𝗼𝘃𝗲𝗺𝗲𝗻𝘁 𝗮𝘁 𝘀𝗰𝗮𝗹𝗲? Hrishi Sathwane Tarun Verma Harish Wadhwa Dr. Satya Gupta