Techniques to Reduce RF Impedance Using Capacitors

🎯 “Decoupling in High-Frequency Analog — When Cap Size, Placement & Parasitics Start to Matter” At low frequencies, decoupling is a checklist item: 🔹 Add a 0.1 µF cap near the supply 🔹 Done. But in high-frequency analog — VCOs, LNAs, high-speed ADCs — decoupling becomes a discipline. Because what used to be a humble capacitor… now becomes a source of resonance, noise, and failure — if not handled right. --- ⚡ Why High-Frequency Decoupling Is Tricky In the GHz domain: Capacitors are no longer “ideal” — parasitic inductance (ESL) and resistance (ESR) dominate PCB traces behave like transmission lines Supply noise becomes phase noise “Short distances” become effective antennas > A poor decoupling strategy won't just add ripple — it will kill your analog performance silently and unpredictably. --- 🛠️ Smart Decoupling Strategy 🔹 1. Use Capacitors in Parallel — Targeting Different Frequency Bands Use a mix of capacitor values in parallel, each tuned for a different noise range: 10 µF bulk capacitors help stabilize supply at low frequencies (below 1 MHz) 0.1 µF general-purpose caps are effective in the 10–50 MHz range 1 nF capacitors are useful around 100–500 MHz for smoothing fast edges 100 pF RF decoupling caps are effective at GHz frequencies and beyond This technique ensures your power line is clean across the entire noise spectrum. --- 🔹 2. Placement: Loop Area is the Real Enemy The capacitor’s value doesn’t matter much if placed poorly. Keep the current loop area as small as possible Use short, wide traces Prefer vias-in-pad or very close stitching vias Place the cap right next to the supply pin > Think of each capacitor as a fire extinguisher — Useless if it’s down the hall during a fire at your desk. --- 🔹 3. Know Your Parasitics Real-world capacitors have more than capacitance. They come with Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL): High ESR adds voltage ripple during current transients High ESL limits the cap’s effectiveness at high frequencies Beyond the self-resonant frequency, the capacitor starts acting like an inductor 💡 For example, a 0.1 µF capacitor with 1 nH ESL loses effectiveness beyond ~160 MHz. --- 🔹 4. Avoid Unintended Resonance Multiple capacitors in parallel can unintentionally create LC tank circuits, leading to impedance spikes — not dips. To flatten the response: Add small series resistors (~1–2 Ω) Use ferrite beads between blocks Avoid clustering too many identical cap values in one place --- 🔹 5. Ground and Power Planes Matter Don’t just focus on VDD — the return path (ground) is equally critical: Use solid, low-impedance ground planes Don’t let digital return currents share the analog ground Use stitched grounds and separate analog/digital regions carefully > Clean VDD with a noisy GND still leads to performance loss. #AnalogDesign #Decoupling #CapacitorSelection #PowerIntegrity #PDN #RFDesign #GHzCircuits

We’re often told to place decoupling capacitors as close to the IC as possible. But in high-speed design, that advice is an oversimplification. At high frequencies (f), what really matters is the impedance (Z) seen by noise 🔊. ⚡️ And this impedance isn’t determined by resistance 🚧. It’s dominated by the total inductance (Lloop) of the current path 🛣️ and the relationship is straightforward, Z ≈ jωLloop (where ω=2πf) This total loop inductance sets the capacitor’s self-resonant frequency (SRF), the point where it’s most effective. Once you go above its SRF, the capacitor starts behaving like an inductor, making it useless for suppressing high-frequency noise. To effectively tackle high-frequency noise, you need to minimize impedance by reducing the total loop inductance, which consists of, Lloop=Ltrace+Lcap_ESL+Lvia Focusing only on shortening the trace (L_trace) by a few millimeters often overlooks the bigger culprit: L_via ❌. The real objective is to shrink the entire loop area, which typically means prioritizing via placement 📌 to ensure the most direct connection 🛣️ to the ground plane 🟦. A well-placed via can be more critical than simply placing the capacitor physically close to the IC. ✅ The correct approach: First, determine the optimal via positions to create the shortest, most direct path from the capacitor pads to the power and ground planes. Then, place the capacitor in that optimal spot as close as practical to the IC power pins to keep the total loop inductance as low as possible. And don't Forget the Capacitor ESL. 🎯 Stop thinking in millimeters 📏. Start designing in nanohenries 🔬. #PowerIntegrity #SignalIntegrity #CircuitDesign #PCBDesign #HighSpeedDesign #EMC #EMI #ElectronicEngineering

🙄 Debunking a Decades-Old Myth: The "3 Capacitor Values" Rule For years, we've followed the "rule" of placing three different decoupling capacitor values: 0.1µF, 0.01µF, 0.001µF or more commonly 10µF/1µF /0.1µF on each power pin to cover a broad frequency range. The idea was simple: larger caps handle low frequencies, smaller ones take care of high frequencies. This guideline appears in countless schematics and datasheets. But as explained in this eye-opening article by Eric Bogatin, Larry Smith, and Steven Sandler ("The Myth of Three Capacitor Values" – Signal Integrity Journal), this is largely a myth in modern designs. The rule originated in the through-hole era, where smaller-value ceramic disk capacitors had shorter leads → lower ESL→ better high-frequency performance. With today's MLCCs, dominant for >20 years, capacitance is decoupled from package size. A 10µF and a 0.1µF MLCC in the same footprint have nearly identical ESL (often <1nH with good layout). Result? High-frequency performance is dominated by mounting inductance (loop area, via placement, routing), not the capacitance value. Using widely spaced values often creates unwanted parallel resonance peaks in the impedance profile potentially worsening noise! Simulations show that multiple identical higher-value MLCCs (e.g., several 10µF) can yield a flatter, better impedance curve. So how should we select capacitor values today? There is no universal magic set of three values. The right answer is: Prioritize lowest possible ESL through smart placement (as close as possible, short power/ground paths, vias-in-pad if needed). For single-cap situations (low-current pins): Use the highest capacitance in the smallest practical package e.g., 1–10µF in 0402/0603. For multiples: Consider identical values to avoid resonances, or model the full PDN. Always aim for a flat, low target impedance profile across the needed frequency range, this requires system-level analysis (VRM, package, die effects), not blind rules. Bottom line: Stop blindly applying 50-year-old guidelines. Analyze your PDN, optimize layout for low inductance, and test thoroughly. 🤔 What outdated "rules" have you recently questioned in your designs? #PowerIntegrity #DecouplingCapacitors #PCBDesign #SignalIntegrity

Back to Basics: 3 Terminal Capacitors Many of you might not have heard or used this one. Let's see what the heck these are today. 3-Terminal Capacitors (Technically it's a 4 terminal one.) is an MLCC whose internal electrodes are arranged as a feedthrough 2-port (Check Images). Your signal enters on one end, exits on the other, and the third terminal is a ground plate. In many packages, ground is split into two pads, so you see 4 pads, but both ground pads are the same node. Why do this then? In a normal 2-terminal decoupling cap connected to ground, the high-frequency current has to go through pads, vias, and plane. That loop inductance(ESL) is often a limiting factor. A 3-terminal part forces the line to pass through the component while giving the noise a short, symmetric path to ground. That reduces effective ESL. If you look at the attenuation curves, the difference is very clear. A 3-terminal part keeps behaving like a real capacitor much higher in frequency because its effective ESL is far lower. You can try to approximate it by placing two normal capacitors in parallel, but that rarely fixes the core problem, which is the loop inductance. In practice, one 3-terminal capacitor can deliver the same high-frequency suppression you’d otherwise get with several 2-terminal caps in parallel. A 3-terminal capacitor is useful when you need better noise filtering at high frequencies, not just more capacitance. It works well at boundaries, like where a buck regulator feeds an RF module, a camera or sensor section, or where power enters a shield can or connector. The big advantage is that it can reduce high-frequency noise with fewer parts and more predictable results. The downsides are higher cost, limited values and current ratings, and it only works well if you place it correctly with a very solid ground connection. There’s a lot more to using these in real circuits, including placement, grounding, and how to choose the right part etc. I can’t fit all of that here due to the post character limit. If there’s genuine interest, I’ll do a follow-up post. #BackToBasics #Electronics