Day 1 at FWD26 was nothing short of incredible. There’s something powerful about being in a room filled with builders, thinkers, and leaders who are all pushing the boundaries of what’s possible. The energy was high, and the ideas shared were both practical and visionary. The keynote sessions truly set the tone. Renen Hallak’s talk was a masterclass in clarity and vision. He didn’t just share insights — he challenged us to think bigger, move faster, and embrace what's coming. His perspective on innovation and the thinking machine was grounding and motivating. Jeff Denworth brought a bold and refreshing lens on the future of technology and scale. His insights on building, navigating exponential change were packed with real-world wisdom. The competitive comparison against industry standards were mind blowing. It wasn’t theory — it was hard-earned experience delivered with authenticity (and Jeff being Jeff: with loads of fun). Grateful to be here and excited for what Day 2 brings.

John Mao dives deeper into our new CNode-X annoucement. A lot of the AI industry today is still built on fragmented infrastructure — separate systems for storage, data pipelines, and GPU compute. That’s exactly what makes the CNode-X announcement from VAST Data and NVIDIA so important. With CNode-X, we’re taking a major step toward a unified, fully accelerated AI data stack: • Integrating GPU-accelerated compute directly into the VAST AI OS • Accelerating core data services like SQL analytics and vector search (SQL Queries that used to run in seconds, now takes milliseconds) • Bringing AI pipelines (embedding, video, and unstructured data processing) directly into the platform • Helping enterprises keep GPUs fully utilized while scaling AI training and inference The industry is moving away from stitched-together components and toward integrated AI systems that simplify how organizations build AI factories. CNode-X is a big step in that direction — enabling organizations to move faster from data → intelligence → outcomes. More details on the announcement: https://lnkd.in/gSeisxp3 #AI #ArtificialIntelligence #GPUComputing #AIInfrastructure #DataPlatform #NVIDIA #VASTData #AIStack #EnterpriseAI #MachineLearning

A defining moment in the age of data computing. VAST Data is closer that ever in getting closer in building a thinking machine. The collaboraion between VAST & NVIDIA in bringing a new ages of software infrastructure is just epic. #inference #AI #software #AcceleratedComputing

x86 vs ARM CPUs Data centers are evolving fast, and it’s no longer just about speed. Power efficiency, AI workloads, and long-term CPU availability are reshaping infrastructure decisions in 2026. Which architecture is actually gaining ground? Read the full article to find out: https://lnkd.in/exTh-wh7 • • • #datacenters #x86 #arm #aiinfrasctucture #microchipusa #longtermsupplier #electroniccomponents #usasupplier

🚀 NVIDIA just showed the future of inference at GTC 2026 — and it’s heterogeneous. Jensen Huang unveiled the Groq 3 LPX platform today: 128 LPUs co-designed with Vera Rubin NVL72 GPUs, delivering 35× higher throughput per megawatt. The message is clear — the next era of inference is about combining different chip architectures, each doing what it does best. And real-world datacenters go even further. Most clusters already hold GPUs from multiple vendors, generations, and architectures — NVIDIA alongside AMD, last-gen nodes next to new deployments. The opportunity is enormous, but traditional inference software can’t serve them together. 🧩 That’s what MoAI Inference Framework was built for. Moreh’s software unifies NVIDIA, AMD, Tenstorrent, and legacy GPUs into a single inference cluster behind one API — splitting prefill and decode across vendors, routing workloads intelligently, and keeping every GPU productive. ⚡ The heterogeneous compute era is here. We make sure your whole fleet is part of it. 🔥 🔗 https://lnkd.in/gWi2RiZy #GTC2026 #NVIDIA #AIInference #HeterogeneousComputing #LLMInference #MLInfrastructure #AIInfrastructure #GPU #Moreh #MoAI

Spent some time recently understanding how Kubernetes actually uses CPU under the hood, and I wanted to share a simple breakdown of what I learned.

Introducing GLYPH — a clean-slate computer architecture built for high-performance emulation, virtualization, and portable deployment. A standout feature is an integrated network-on-chip that supports reliable multicast for thread-group signaling. It is designed to map closely to Intel/AMD x86, with an expanded register file and a software-defined MMU. 📂 Repo: https://lnkd.in/ec7c9cSj 📘 Doc: https://lnkd.in/eZdERC_R #ComputerArchitecture #VirtualMachines #Emulation #SystemsDesign

When AI is part of a server refresh conversation, a few technical realities start to matter more than they used to: • AI workloads move large volumes of data, often exposing memory and I/O bottlenecks before CPU limits • CPUs can sit underutilized if the platform can’t move data fast enough to accelerators • Adding GPUs only helps if the surrounding architecture can keep them fed • Power and cooling constraints on older servers can cap density sooner than expected • Platform-level security and firmware integrity become more relevant as stacks grow more complex This VLCM blog breaks down how modern server platforms are being designed around these considerations, using HPE ProLiant Gen11 and Gen12 as examples of where compute is heading as AI workloads become more common. Read the post: https://lnkd.in/gR_F2xni

At the top level, a GPU chip is made up of many Streaming Multiprocessors (SMs). Think of SMs as mini parallel engines replicated across the chip. Instead of one big brain, you get dozens of smaller ones working simultaneously. Inside each SM: 🔹A Warp Scheduler decides which group of threads (a warp) runs next. 🔹Dozens of CUDA Cores execute instructions in parallel. 🔹A Register File stores thread-local data at ultra-low latency. 🔹Load/Store units move data between registers and memory. 🔹Texture units handle specialized memory operations. 🔹L1 Cache provides fast, on-SM data access. Each SM works independently, but they’re connected through an on-chip interconnect. Below that sits the L2 Cache, shared across all SMs. This is the coordination layer. If one SM misses in L1, it checks L2 before going to global memory. Then come the Memory Controllers, which interface with Global Memory. This is where things get interesting: Extremely high bandwidth Much higher latency than on-chip memory That’s why GPUs rely on massive parallelism. While some threads wait on memory, thousands of others keep executing. #SystemDesign #TechSuccess #EngineeringExcellence #learning #softwaredevelopment #webdevelopment #database #servers ImgCredit: ByteByteGo

x86’s SIMD evolution is a compatibility nightmare. Every new vector width (SSE → AVX → AVX-512) requires completely different code. Libraries ship 3-4 versions of every optimized function. Your AVX-512 code runs on less than 20% of x86 CPUs. RISC-V Vector Extension solves this with length-agnostic design. Write once, run anywhere: ∙ Same binary on 128-bit embedded chips ∙ Same binary on 256-bit general-purpose cores ∙ Same binary on 512-bit HPC processors ∙ Same binary on 1024-bit supercomputers The hardware adapts automatically. No recompilation. No multiple code paths. No runtime CPU detection. Performance scales linearly with hardware width: ∙ 128-bit: 4× speedup ∙ 256-bit: 8× speedup ∙ 512-bit: 16× speedup Simpler than ARM SVE. Open standard, no vendor lock-in. Already shipping in commercial silicon (Alibaba, SiFive, SpacemiT). I wrote a complete technical breakdown covering: ∙ Application Vector Length abstraction ∙ Register grouping (LMUL) ∙ Real assembly code examples ∙ Performance benchmarks ∙ Hardware implementations What’s your experience with SIMD? AVX, NEON, or SVE? #RISCV #ComputerArchitecture #SIMD #VectorProcessing #HPC Full deep-dive: