Synopsys CEO on AI's impact on engineering

I asked the CEO of Synopsys Inc about the future of AI and software engineering. Here is what Sassine Ghazi said: 1. Optimize the whole stack Don’t just code. Engineer the whole stack. Understand how silicon, software, systems, and AI work interdependently. Your level of expertise will pay dividends when others hit their limits. 2. AI cuts toil, not engineers AI is already designing chips, testing code, and writing documentation. As AI advances, the demand for complex systems grows faster than the talent pool. By 2030, the tech market will face a shortage of over 1 𝗺𝗶𝗹𝗹𝗶𝗼𝗻 𝗲𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝘀. 3. Go deep in one domain, not wide in ten Most students chase new frameworks instead of mastering one field deeply. Depth creates insight, and insight creates innovation. The best engineers can even explain the physics behind their code. The future belongs to those who understand deeper, not code faster. ♻️ Repost to help others understand the future of AI and engineering.

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💡 Synopsys Inc 𝐮𝐧𝐯𝐞𝐢𝐥𝐬 𝐕𝐒𝐎.𝐀𝐈 – 𝐀𝐈-𝐝𝐫𝐢𝐯𝐞𝐧 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐎𝐩𝐭𝐢𝐦𝐢𝐳𝐚𝐭𝐢𝐨𝐧 🚀 Verification consumes nearly 70% of chip design effort, and Synopsys has built this to tackle this bottleneck using the power of AI. 🔹 Why This Matters: • Verification regressions are massive – millions of tests, huge compute cost. • Intelligently identifies redundant tests and coverage holes. • Results show up to 10× faster coverage convergence and ~30% higher verification productivity. • Frees engineers to focus on debugging and design quality, not endless simulation. ⚙️ Key Features: • AI-powered regression optimization – selects only the most valuable tests to run. • Coverage inference – predicts untested logic regions and guides stimulus generation. • Root cause analysis – finds unreachable states and constraint conflicts automatically. • Easy integration – works with existing flows (like Synopsys VCS) without major setup changes. 📎 Read more: https://lnkd.in/gCMPN2eS 💬 𝐅𝐨𝐫 𝐦𝐨𝐫𝐞 𝐕𝐋𝐒𝐈 𝐫𝐞𝐬𝐨𝐮𝐫𝐜𝐞𝐬, 𝐣𝐨𝐛 𝐮𝐩𝐝𝐚𝐭𝐞𝐬, 𝐚𝐧𝐝 𝐢𝐧𝐝𝐮𝐬𝐭𝐫𝐲 𝐢𝐧𝐬𝐢𝐠𝐡𝐭𝐬 – 𝐣𝐨𝐢𝐧 𝐨𝐮𝐫 𝐖𝐡𝐚𝐭𝐬𝐀𝐩𝐩 𝐜𝐡𝐚𝐧𝐧𝐞𝐥: https://lnkd.in/gqzzZYBZ #Synopsys #VSOai #AIinEDA #Verification #ChipDesign #SoC #VLSI #Semiconductors #DigitalDesign

Everything in Science actually falls into 4 layers Across domains, I think we can group everything we build into: * Science – Fundamental truths, natural laws * Technology – Scientific principles packaged into usable artifacts * Engineering – Systematic way to apply technology * Application – Solving real world problems using engineered systems Let me explain this with a simple IT example 👇 * Semiconductor physics → is Science * ICs / CPUs / Chips → is Technology built on that science * Programming Languages / Compilers / OS → is Engineering built on top of tech * Software Products / Apps / Platforms → is Application that solves a problem So when we build software, we are actually building applications sitting on top of multiple layers of engineering → which itself sits on technology → which sits on science. All innovation basically climbs this ladder. This is why I believe: Deep tech leaders need mental models that span all 4 layers — not just “application building”. Because when we understand the lower layers → our ability to innovate at the top layer increases dramatically. Curious to hear from other engineering leaders — 👉 Do you think this 4-layer model fits for other domains beyond IT too? (e.g. Healthcare, Energy, EVs, AI etc.) #EngineeringLeadership #SystemsThinking #DeepTech #Innovation #ProductThinking #TechPhilosophy #FintechLeader

At Pure Silicon, our strength lies in our experts, who turn complex verification challenges into elegant solutions. Get to know Lead Formal Verification Engineer Antonio Anastasio Bruto da Costa in the following Q&A! 1. What’s your current focus area at Pure Silicon, and what types of projects or developing technologies are you most excited about right now? I'm always focused on further upskilling in #formalverification to be better equipped to tackle problems I’ve never seen before. This often means applying my skills to “practice IP” to explore niche aspects of digital IP verification. In parallel, I create content to make formal verification more approachable for a range of audiences in the #semiconductor space. I’m also evaluating emerging #AI‑assisted formal verification tools, which I believe will play a transformative role in the future of verification. 2. What’s one engineering challenge you’ve solved recently that you’re especially proud of? I verified a #controller that interacted with multiple memories. The key was developing a #verification solution that didn’t require instantiating the memories themselves. This approach significantly accelerated #convergence. Beyond the technical win, I also focused on documenting the solution in a way that was clear not only for my team but also for customers—turning a complex problem into a teachable resource. 3. How do you see chip design or verification evolving over the next few years? I see formal verification becoming increasingly central to #chipdesign over the next few years. As designs grow in complexity, #simulation alone won’t be enough to guarantee correctness. What excites me is the convergence of formal methods with AI assistance. Instead of replacing engineers, I believe AI will act as a force multiplier, helping us explore state spaces faster, generate assertions, and even suggest abstractions we might not have considered. This shift could democratize formal verification, making it more accessible to #engineers who may not have specialized in it, and ultimately raising the baseline of verification quality across industry. 4. What’s one tool, method, or mindset that you think gives engineers an edge in tackling complex #SoC or IP verification problems? The ability to compartmentalize. Breaking down an IP’s function into manageable categories makes it less overwhelming to formally model. By simplifying the problem space, you not only make progress faster, but also build confidence in the correctness of each piece before scaling up to the full design. 5. When you’re not deep in waveforms or code, what do you enjoy doing outside of work? I enjoy playing the piano and exploring Birmingham, England—a city with more canals than Venice! I also love cooking, and lately I’ve been experimenting with vegan cuisine. Re‑imagining traditional Goan and Indian dishes in plant‑based form has become a creative passion of mine.

𝐈𝐧𝐭𝐫𝐨𝐝𝐮𝐜𝐢𝐧𝐠 𝐕𝐒𝐎.𝐚𝐢 - 𝐀𝐈-𝐃𝐫𝐢𝐯𝐞𝐧 𝐕𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐟𝐨𝐫 𝐅𝐚𝐬𝐭𝐞𝐫 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐂𝐥𝐨𝐬𝐮𝐫𝐞! As semiconductor designs scale in complexity, verification teams face immense pressure to achieve thorough coverage, catch more bugs early, and close verification faster. VSO.ai addresses these challenges with 𝐚𝐝𝐯𝐚𝐧𝐜𝐞𝐝 𝐀𝐈/𝐌𝐋 techniques. 𝐖𝐡𝐚𝐭 𝐕𝐒𝐎.𝐚𝐢 𝐃𝐨𝐞𝐬? 🔹 Infers additional coverage from RTL + stimulus, beyond manually defined coverage points. 🔹 Optimises regression test sequencing by running high-ROI tests first and eliminating redundant runs. 🔹 Performs root-cause analysis (RCA) of coverage holes: identifies why certain bins remain unhit (e.g., constraint issues, stimulus gaps) and presents actionable insights. 🔹 Integrates with existing verification flows (e.g., the VCS simulator environment) with minimal changes required to design/testbench. 𝐊𝐞𝐲 𝐁𝐞𝐧𝐞𝐟𝐢𝐭𝐬 𝟏. Helps reach 𝐡𝐢𝐠𝐡 𝐪𝐮𝐚𝐥𝐢𝐭𝐲 𝐜𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐢𝐧 𝐥𝐞𝐬𝐬 𝐭𝐢𝐦𝐞 𝐚𝐧𝐝 𝐰𝐢𝐭𝐡 𝐟𝐞𝐰𝐞𝐫 𝐫𝐮𝐧𝐬. Example: On a PCIe Gen6 PHY regression, the same functional coverage (61 %) was achieved in ~3× fewer runs. 𝟐. 𝐄𝐧𝐚𝐛𝐥𝐞𝐬 𝐩𝐫𝐨𝐝𝐮𝐜𝐭𝐢𝐯𝐢𝐭𝐲 𝐢𝐦𝐩𝐫𝐨𝐯𝐞𝐦𝐞𝐧𝐭𝐬: users report up to 10× reduction in functional coverage holes and up to ~30% improvement in IP verification productivity. 𝟑. Allows engineers to shift focus from running regressions to analysing results and debugging - improving verification efficiency and quality. 𝐖𝐡𝐲 𝐭𝐡𝐢𝐬 𝐦𝐚𝐭𝐭𝐞𝐫𝐬? With shrinking time-to-market windows and rising verification resource demands (compute, human effort), adopting AI-enabled verification flows like VSO.ai becomes a differentiated capability. It essentially helps verification teams do smarter-not necessarily more-work, thereby accelerating sign-off readiness and improving confidence in the design’s quality. #SemiconductorVerification #EDA #VLSI #FunctionalVerification #Synopsys #VSOai #AI #VerificationEngineering #CoverageClosure #TheSiliconSandbox

As chip complexity outpaces Moore's Law, the pressure for first-pass silicon success is immense. RTL signoff is no longer a simple linting exercise; it's a strategic imperative. The goal has shifted from finding bugs to preventing them from ever reaching synthesis. Here are the five key trends shaping the future of RTL signoff: 1. AI-Driven Verification: Machine learning is being deployed to predict design hotspots, prioritize checks, and accelerate root cause analysis, intelligently navigating massive design spaces. 2. Intensified Shift-Left: More complex, implementation-aware checks (e.g., clock domain crossing, power intent, congestion) are moving from post-synthesis into the RTL domain, catching costly bugs months earlier. 3. Mainstreaming Formal Methods: Once a specialist tool, formal verification is becoming standard for providing exhaustive mathematical proofs on critical IP, security logic, and complex state machines where simulation falls short. 4. Cloud-Native EDA Flows: The elasticity of the cloud is enabling teams to run massive-scale regressions and deploy advanced analyses on-demand, breaking the constraints of on-premise compute farms. 5. Domain-Specific Signoff: Generic rule sets are giving way to specialized checks tailored for automotive (ISO 26262), AI/ML architectures, and security vulnerabilities, ensuring compliance and robustness from the start. These trends represent a fundamental rethinking of how we manage risk and ensure quality at the most leveraged stage of chip design. #RTLSignoff #EDA #Semiconductors #ChipDesign

ChipAgents raises $21M Series A to bring agentic #AI to chip design and verification ChipAgents, a Santa Barbara–based AI platform reimagining chip design and verification, has raised $21M in Series A funding, bringing its total funding to $24M. The round was led by Bessemer Venture Partners, with participation from Micron Ventures, MediaTek, Ericsson, and other semiconductor leaders, alongside angels including Wally Rhines, Raúl Camposano, and Jack Harding. Founded by Professor William Wang, ChipAgents is building agentic AI systems that enable hardware companies to define, validate, and refine RTL code—simplifying complex workflows and driving new levels of productivity and accuracy. With a newly formed advisory board featuring legends from Mentor Graphics, Synopsys, and Cadence, the company is poised to redefine how silicon is designed in the AI era. William Yang Wang - CEO & Founder Mehir Arora- Head of Engineerin @Kexun Zhang - Head of Research Jeffrey Critten - VP of Strategic Accounts Jian Gao - Sr. Software Engineer Zackary Glazewski - ML Engineer David Wang - ML Engineer Danny Rose- ML Engineer Noah Wang - ML Engineer Kanav Arora- ML Engineer Samuel Zhu - ML Engineer Tanay B. - ML Researcher Surya Gunukula - ML Researcher Minh Bui - Hardware Engineer Torin Schlunk - Application Engineer Luke Frey - Application Engineer Jonathan Thomas - Application Engineer #AI #Semiconductors #EDA #ChipDesign #AgenticAI #VentureCapital #StartupFunding #HardwareEngineering #DeepTech #ChipAgents #Innovation

ChipAgents Raises $21 Million for Agentic Chip Design - EE Times: Customers' prompts, queries and usage data are also kept private, Wang said. ChipAgents' 50 customers include many big semiconductor players, Wang ... #bigdata #cdo #cto