How Northrop Grumman cut CDC verification time by 75% with Siemens EDA

Clocking in with confidence — and cutting verification time by 75%. When your chip design has 30, 40, or even 50 asynchronous clocks, verifying that they all communicate correctly isn’t just a challenge — it’s a mission-critical necessity. As Lisa from Northrop Grumman put it: “Clock analysis can be very difficult and time consuming, and we want to identify any issues early in the design process.” Northrop Grumman’s microelectronics team partnered with Siemens EDA to tackle this challenge head-on. By customizing our AI/ML-powered Clock Domain Crossing (CDC) analysis tool (part of the Questa One Smart Verification solution) they reduced clock analysis time from eight weeks to just two. That’s not just faster verification. That’s faster innovation. With Siemens’ stimulus-free CDC and Reset Domain Crossing (RDC) technology, teams can identify and resolve asynchronous clock issues early, keeping programs on schedule and within budget, even as designs grow more complex. 🔗 Learn how Siemens EDA helped Northrop Grumman accelerate design cycles and push the boundaries of what’s possible in space, defense, and beyond. https://sie.ag/3xXten 🔗 Discover Questa One CDC Verification https://sie.ag/3CqE4X #SmartVerification #CDCAnalysis #DesignEfficiency

Clocking in with confidence — and cutting verification time by 75%. When your chip design has 30, 40, or even 50 asynchronous clocks, verifying that they all communicate correctly isn’t just a challenge — it’s a mission-critical necessity. As Lisa from Northrop Grumman put it: “Clock analysis can be very difficult and time consuming, and we want to identify any issues early in the design process.” Northrop Grumman’s microelectronics team partnered with Siemens EDA to tackle this challenge head-on. By customizing our AI/ML-powered Clock Domain Crossing (CDC) analysis tool (part of the Questa One Smart Verification solution) they reduced clock analysis time from eight weeks to just two. That’s not just faster verification. That’s faster innovation. With Siemens’ stimulus-free CDC and Reset Domain Crossing (RDC) technology, teams can identify and resolve asynchronous clock issues early, keeping programs on schedule and within budget, even as designs grow more complex. 🔗 Learn how Siemens EDA helped Northrop Grumman accelerate design cycles and push the boundaries of what’s possible in space, defense, and beyond. https://sie.ag/3xXten 🔗 Discover Questa One CDC Verification https://sie.ag/3CqE4X #SmartVerification #CDCAnalysis #DesignEfficiency

Clocking in with confidence — and cutting verification time by 75%. When your chip design has 30, 40, or even 50 asynchronous clocks, verifying that they all communicate correctly isn’t just a challenge — it’s a mission-critical necessity. As Lisa from Northrop Grumman put it: “Clock analysis can be very difficult and time consuming, and we want to identify any issues early in the design process.” Northrop Grumman’s microelectronics team partnered with Siemens EDA to tackle this challenge head-on. By customizing our AI/ML-powered Clock Domain Crossing (CDC) analysis tool (part of the Questa One Smart Verification solution) they reduced clock analysis time from eight weeks to just two. That’s not just faster verification. That’s faster innovation. With Siemens’ stimulus-free CDC and Reset Domain Crossing (RDC) technology, teams can identify and resolve asynchronous clock issues early, keeping programs on schedule and within budget, even as designs grow more complex. 🔗 Learn how Siemens EDA helped Northrop Grumman accelerate design cycles and push the boundaries of what’s possible in space, defense, and beyond. https://sie.ag/3xXten 🔗 Discover Questa One CDC Verification https://sie.ag/3CqE4X #SmartVerification #CDCAnalysis #DesignEfficiency

Clocking in with confidence — and cutting verification time by 75%. When your chip design has 30, 40, or even 50 asynchronous clocks, verifying that they all communicate correctly isn’t just a challenge — it’s a mission-critical necessity. As Lisa from Northrop Grumman put it: “Clock analysis can be very difficult and time consuming, and we want to identify any issues early in the design process.” Northrop Grumman’s microelectronics team partnered with Siemens EDA to tackle this challenge head-on. By customizing our AI/ML-powered Clock Domain Crossing (CDC) analysis tool (part of the Questa One Smart Verification solution) they reduced clock analysis time from eight weeks to just two. That’s not just faster verification. That’s faster innovation. With Siemens’ stimulus-free CDC and Reset Domain Crossing (RDC) technology, teams can identify and resolve asynchronous clock issues early, keeping programs on schedule and within budget, even as designs grow more complex. 🔗 Learn how Siemens EDA helped Northrop Grumman accelerate design cycles and push the boundaries of what’s possible in space, defense, and beyond. https://sie.ag/3xXten 🔗 Discover Questa One CDC Verification https://sie.ag/3CqE4X #SmartVerification #CDCAnalysis #DesignEfficiency

Clocking in with confidence — and cutting verification time by 75%. When your chip design has 30, 40, or even 50 asynchronous clocks, verifying that they all communicate correctly isn’t just a challenge — it’s a mission-critical necessity. As Lisa from Northrop Grumman put it: “Clock analysis can be very difficult and time consuming, and we want to identify any issues early in the design process.” Northrop Grumman’s microelectronics team partnered with Siemens EDA to tackle this challenge head-on. By customizing our AI/ML-powered Clock Domain Crossing (CDC) analysis tool (part of the Questa One Smart Verification solution) they reduced clock analysis time from eight weeks to just two. That’s not just faster verification. That’s faster innovation. With Siemens’ stimulus-free CDC and Reset Domain Crossing (RDC) technology, teams can identify and resolve asynchronous clock issues early, keeping programs on schedule and within budget, even as designs grow more complex. 🔗 Learn how Siemens EDA helped Northrop Grumman accelerate design cycles and push the boundaries of what’s possible in space, defense, and beyond. https://sie.ag/3xXten 🔗 Discover Questa One CDC Verification https://sie.ag/3CqE4X #SmartVerification #CDCAnalysis #DesignEfficiency

Clocking in with confidence — and cutting verification time by 75%. When your chip design has 30, 40, or even 50 asynchronous clocks, verifying that they all communicate correctly isn’t just a challenge — it’s a mission-critical necessity. As Lisa from Northrop Grumman put it: “Clock analysis can be very difficult and time consuming, and we want to identify any issues early in the design process.” Northrop Grumman’s microelectronics team partnered with Siemens EDA to tackle this challenge head-on. By customizing our AI/ML-powered Clock Domain Crossing (CDC) analysis tool (part of the Questa One Smart Verification solution) they reduced clock analysis time from eight weeks to just two. That’s not just faster verification. That’s faster innovation. With Siemens’ stimulus-free CDC and Reset Domain Crossing (RDC) technology, teams can identify and resolve asynchronous clock issues early, keeping programs on schedule and within budget, even as designs grow more complex. 🔗 Learn how Siemens EDA helped Northrop Grumman accelerate design cycles and push the boundaries of what’s possible in space, defense, and beyond. https://sie.ag/3xXten 🔗 Discover Questa One CDC Verification https://sie.ag/3CqE4X #SmartVerification #CDCAnalysis #DesignEfficiency

Whether you’re testing AI GPUs, protecting them in data centers and AI factories, powering next-gen manufacturing lines, or engineering mission-critical aerospace and defense systems — reliable, high-performance switching technology is the foundation of progress. At Menlo Micro, we’re setting a new standard in electronic switching with the Ideal Switch®, combining the speed and reliability of a semiconductor with the power-handling capability of an electromechanical relay. The result: a new era of high performance, efficiency, and scalability in system design. To stay informed on how the #IdealSwitch is advancing T&M, A&D and Power Electronics: 🔹 Subscribe to our newsletter for insights into the latest innovations, collaborations, and product developments: 👉Subscribe here: https://lnkd.in/g4ZU8jz2 To equip your engineering team with immediate access to technical resources and support: 🔹 Create a free account on the Menlo Support Portal: 👉 Sign up here: https://lnkd.in/g_u7SwKE #IdealSwitch #AIHardware #DataCenters #PowerDistribution #Aerospace #Defense #Innovation #MenloMicro

𝐂𝐨𝐦𝐩𝐚𝐫𝐢𝐧𝐠 𝐀𝐓 𝐒𝐢𝐭𝐞𝐬 𝐟𝐨𝐫 𝐏𝐡𝐨𝐭𝐨𝐧𝐢𝐜𝐬 𝐚𝐧𝐝 𝐒𝐢𝐥𝐢𝐜𝐨𝐧 𝐈𝐂𝐬 𝐄𝐯𝐞𝐫𝐲 𝐬𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐣𝐨𝐮𝐫𝐧𝐞𝐲 𝐛𝐞𝐠𝐢𝐧𝐬 𝐢𝐧 𝐚 𝐟𝐚𝐛, 𝐛𝐮𝐭 𝐢𝐭 𝐝𝐨𝐞𝐬𝐧’𝐭 𝐞𝐧𝐝 𝐭𝐡𝐞𝐫𝐞. Once wafers are built, they travel to a new stage of transformation — the Assembly & Test (AT) site. It’s here that chips are packaged, connected, and validated before they’re deployed into servers, cars, or systems. Think of it as the final proving ground — where the precision of design meets the realities of manufacturing. And this is where photonics changes everything. 𝐒𝐢𝐥𝐢𝐜𝐨𝐧 𝐄𝐥𝐞𝐜𝐭𝐫𝐨𝐧𝐢𝐜𝐬 (𝐈𝐂𝐬) 𝐯𝐬 𝐏𝐡𝐨𝐭𝐨𝐧𝐢𝐜𝐬 (𝐏𝐈𝐂𝐬) 𝐚𝐭 𝐭𝐡𝐞 𝐀𝐓 𝐬𝐢𝐭𝐞 Primary Goal • Electrical interconnect and signal integrity • Optical alignment and coupling efficiency Assembly Precision • Micron-level • Sub-micron (angular + positional) Critical Interface • Wire bonding / flip chip • Fiber attach / laser alignment / waveguide coupling Testing Focus • Electrical parametrics, timing, leakage • Optical power, wavelength, insertion loss Automation Level • High, mature • Mixed — automation + manual alignment Yield Drivers • Bond quality, thermal cycles • Coupling accuracy, photonic-electronic co-planarity #SiliconPhotonics #Photonics #Semiconductors #AssemblyAndTest #Manufacturing #OpticalIO #Datacenters #AIInfrastructure #FutureOfCompute

When Semiconductor Manufacturing Nears Its Physical Limit, Temperature Control Becomes the Last Line of Defense In the semiconductor world, temperature is not just a number — it’s the boundary between precision and failure. As process nodes shrink to 2 nm and beyond, even a 0.01 °C fluctuation can affect yield, performance, and reliability. From photolithography and etching to packaging and testing, Coolingstyle’s precision chillers maintain stable environments ranging from –55 °C to 150 °C, enabling consistent results across every stage of semiconductor production. In the era of AI acceleration and high-bandwidth memory, Coolingstyle continues to pioneer micro-environment cooling technologies — pushing the limits of accuracy and redefining thermal stability for the future of chips. #Semiconductor #TemperatureControl #PrecisionCooling #AIChips #Coolingstyle #ManufacturingInnovation

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