From the course: Learning Verilog for FPGA Development
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Registers and wires - FPGA Tutorial
From the course: Learning Verilog for FPGA Development
Registers and wires
- [Instructor] So far you've seen code with wires. It turns out, wires are one type of element. You may use to make connections in Verilog. The other type are registers. So, let me tell you the difference between theses types. Wires make connections between elements. They implement nets. Otherwise known as nodes in the circuit. Since wires are simply nets. They are driven by signals. They may not always have a value. So, they may have a high impedance or High-Z state. Which is neither a zero or one. But, equivalent to a floating node. Registers on the other hand. Can also make connections between elements in the code. But, registers can be a assign values. And they hold those values until the next assignment. And finally registers can drive wires. Just a quick warning! The name register is misleading. Because Verilog registers do not necessary produce. Flip flops in a FBA or ASIC implementation. Consider a wire A and…
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Contents
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Verilog modules4m 13s
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(Locked)
Instantiating modules4m 49s
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(Locked)
Gates and primitives3m 3s
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(Locked)
Registers and wires1m 46s
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(Locked)
Range specification4m 30s
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(Locked)
Numbers and constants4m 53s
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(Locked)
Always blocks52s
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(Locked)
The if-else statement2m 2s
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(Locked)
Case statements2m 24s
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(Locked)
Boolean algebra expressions56s
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(Locked)
Continuous assignments2m 23s
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(Locked)
Blocking assignments3m 20s
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(Locked)
Nonblocking assignments3m 49s
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(Locked)
Challenge: From schematic to code2m 16s
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(Locked)
Solution: From schematic to code4m 31s
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