Verilog primer - FPGA Tutorial

- In most of the next videos I'll show you some examples in Verilog, so here's a quick description of the basic elements of this language for you to get familiar with it. We'll quickly talk about modules, declarations, primitives, concurrent elements, and control statements. As we saw earlier, a module declaration consists of the module keyword followed by the name of the module and a port list. Here we have a four bit adder, which takes as input a four bit number A, a four bit number B, which are the addition upper ends, and then its outputs are a four bit number S, which contains the results of the addition, and one bit number Co, which is the carry output bit. Notice that both outputs are defined as registers with the reg keyword. Registers in Verilog are data storage units, so they can hold a value assigned to them. The definition of a module is terminated with the endmodule keyword. Let's take a look at some examples of declaration in Verilog. There are two types of signal indentifiers in Verilog. The wire and the register, and that's exactly what they are for, wires, to implement connections between elements and registers to hold values. An important difference is that wires are passive and registers are active. Registers are capable of driving a line, whereas wires take the values from the drivers they are connected to. Here we have the declaration of three wires, X, Y, and Z, and three registers, A, B, and C. Logic gates are available as primitives, like this or gate for example. Notice that you can name your gates if you want. This one is called my or. The port convention for logic gates is that the first port specified is the output, and the rest are the inputs. So this is an or gate, with A and B connected to its inputs and Z to its output. Finally we have an instance declaration of the half adder module we saw recently. Naming your instances is mandatory. This one is called my adder. Once again, gates belong to a set of primitives in Verilog. These include the usual and, or, xor, and not gates, as well as tri-state buffers and transistors. In this example we have four gates connected as shown in the schematic diagram. Take a minute to verify that the code and the schematic match. In Verilog, your code is assumed to describe concurrent elements by default. If you want to define a sequence of events, you need a sequential block, enclosed by the begin and end keywords. There are two concurrent sequential block specifiers. Initial, which specifies that the block works only once, and always @, which specifies that the block operates every time an event condition is met. For example, every time some digital line goes from low to high, known as the positive edge of that line. Finally, control statements are supported in Verilog. Here we have an example of an if then sentence. In this example, some register A is assigned a value of another register B. Then if A equals zero, a third register C is assigned the value zero, otherwise one is assigned to B. At the right we have a case statement in Verilog. In this example we have a two bit register with an always block. The parentheses contains the sensitivity list for the block to operate once. In this example, every time there's a positive edge on a register called C, the case statement will change the value of S. Notice the syntax for binary two bit constants. The number two specifies the bit length of the constant, and the letter B specifies that the number is in binary.