From the course: Learning FPGA Development

Verilog and VHDL - FPGA Tutorial

From the course: Learning FPGA Development

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Verilog and VHDL

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- [Instructor] Now let's see what hardware description languages, or HDLs, are. First, the purpose of an HDL is hardware entry for your toolchain to understand what system you want to produce. A simulator may be used to interpret your code in order to predict its behavior. And later a synthesis tool may be used to implement the design in a field programmable gate array or in an application specific integrated circuit. The built in structure of an HDL based project consists of two categories of modules. Descriptive modules, where you define your hardware and test bench or stimulus modules, where you enter a sequence of inputs to your system. Test bench modules are used by simulators to execute the steps you entered and produce the results you want to see. Here we have two code examples for the same module in Verilog and VHDL. The module is the one shown in the schematic diagram and it's a halfAdder, a basic block to implement a circuit that adds two integers. A halfAdder calculates the addition of a one bit number with another one bit number. If you look at the Verilog code at the left, you'll see that the syntax is somewhat similar to the C programming language. Modules are defined in a similar way to functions in C, but instead of a parameter list they have a port list because remember, this is a hardware module. Notice that this list specifies which port is an input and which port is an output. Next, the body of the module is just two lines of code which are instantiations of an and gate and an xor gate. Notice that the first wire specified is the output and the remaining ones are the inputs. Take your time to read the code and try to understand what it means. At the right we have its equivalent in VHDL, which is a language inspired by the Ada and Pascal programming languages. In VHDL the port list is specified in what is known as an entity and the implementation is defined in an architecture. At this point, I only want you to pay attention to the differences and similarities between these languages. Finally, here's a partial test bench module in both languages describing the same course of events for a simulation. In this example we have two registers named A and B, which both take the value of zero. Then there's a 100 nanosecond pause before assigning one to A and then more assignments are performed on A and B separated by 10 nanosecond pauses. To run this in a simulator, the module must instantiate the halfAdder module we just saw and connect these A and B registers to the A and B inputs of this instance. Simulators usually show the results over time in a waveform viewer.

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