From the course: Getting Started with RISC-V
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CPU registers - Raspberry Pi Tutorial
From the course: Getting Started with RISC-V
CPU registers
- [Instructor] Let's take a look at the CPU Registers in the RV32I base integer ISA. Here are some of its unique characteristics. There are 32 CPU registers named x0 through x31, all of them 32-bits wide. They are all intended for general purpose with one exception. X0 always reads zero and it cannot be overwritten. It is supposed to be hardwired to zero. This has been a design decision since the first drafts of the RISC ISA. Believe it or not, having the constant zero always available in a register simplifies a lot of things in the hardware and in the software. The program counter is a separate register with a specific purpose, to hold the address of the current instruction. This is one of the typical CPU specific purpose registers, but it's the only one in the RISC-V ISA. There is no stack pointer. In consequence, there are no push, pop, subroutine call or return instructions. I know, this may cause some…
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