Austin, Texas, United States
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About

Physical Design Engineer at Ericsson.
An alumnus of Wright State University Major -…

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Experience & Education

  • Qualcomm

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Publications

Courses

  • CMOS Mixed Signal IC Design

    EE7580

  • Control Theory

    -

  • Digital Integrated Circuit Design with PLDs and FPGAs

    EE6620

  • Digital Logic Design

    -

  • Low Power VLSI system design

    EE7520

  • Microcontroller 8051

    -

  • Microprocessor 8085

    -

  • Mixed Signal Tools

    EE8000

  • Trust in Integrated Circuit Design

    EE7550

  • VLSI Circuit Design

    EE6540

  • VLSI Design Synthesis and Optimization

    EE7530

  • VLSI Testing and Design for Testability

    EE7540

Projects

  • Sign-off of the verliog code provided by cadence

    •Produced layouts that functioned at 2+ GHz clock frequencies using timing driven RTL-to-GDSII flow.
    •Performed floorplan-based synthesis of partition logic from RTL, guiding tool to create a netlist that minimized power, route congestion, and area while still achieving timing closure.
    •Ensured that logic created properly implemented isolation, level shifting, and other constraints given the UPF file.
    •Implemented floorplan using best known algorithms and followed by partioning keeping…

    •Produced layouts that functioned at 2+ GHz clock frequencies using timing driven RTL-to-GDSII flow.
    •Performed floorplan-based synthesis of partition logic from RTL, guiding tool to create a netlist that minimized power, route congestion, and area while still achieving timing closure.
    •Ensured that logic created properly implemented isolation, level shifting, and other constraints given the UPF file.
    •Implemented floorplan using best known algorithms and followed by partioning keeping in mind equal number of modules on each partition.
    •Guided layout tool to create a placement that minimized routing problems and met timing, power and other required constraints.
    •Built clock trees using industry standard tools and verified that trees created meet constraints for delay, slope, and skew.

    Tools: Cadence CAD: RTL Compiler, NCSIM, ENCOUNTER

  • High speed and low power implementation of 8x8 Booth multiplier for Digital Matched Filters (DMF)

    •Designed a proposed 8x8 booth multiplier with new architecture consisting of modified BEC in 1st stage instead of adder/subtractor block which consumes less power and area compared to adder/subtractor block with almost same delay.
    •Proposed 8x8 booth multiplier is implemented using SAED32nm technology in custom designer tool by synopsys. The worst case propagation delay and power consumption of design are 420 ps and 0.21 mW at 1 Giga data-rate and transistor count of 4262.

    Tool:…

    •Designed a proposed 8x8 booth multiplier with new architecture consisting of modified BEC in 1st stage instead of adder/subtractor block which consumes less power and area compared to adder/subtractor block with almost same delay.
    •Proposed 8x8 booth multiplier is implemented using SAED32nm technology in custom designer tool by synopsys. The worst case propagation delay and power consumption of design are 420 ps and 0.21 mW at 1 Giga data-rate and transistor count of 4262.

    Tool: Synopsys CAD - Custom Designer, Waveviewer, IC Compiler, Design Compiler and Primetime

  • Implementation of Fiduccia-Mattheyses circuit partitioning algorithm for automatic placement and routing using C++.

    •Implemented a circuit bi-partitioning algorithm using C++ to minimize the cut-set between the partitions while maintaining a desired balance between the sizes of two partitions.
    •Doubly linked list data structure was used in the implementation. gdb was used in the debugging process.
    •An average of 73% cutset reduction was obtained while tested on standard golem benchmarks with consists of 150,000 standard gates.

  • Detection of a Sequence(16-Bit University ID) and Display on FPGA using Finite State Machines .

    Built a Finite State Machine (Both mealy and moore types) using VHDL in Xilinx ISE to detect a se-
    quence and then mapped on to Virtex 6 FPGA to read the output through LCD interface. This project has a counter at the input stage and an adder in the second stage and a sequence detector in the third stage. This project provided me with the necessary experience to work with FPGA and Xilinx tool.

    Tools : ISE Design Suite and Xilinx Virtex-6 FPGA.

  • 2-way set associative Cache Design

    The Entire cache design consisted of SRAM array, Decoders, Dynamic Comparators, Sense Amplifiers Muxes, Hit/Miss logic etc. Cadence with 32nm PDK was used for circuit design and layout. HSPICE was used for simulations at each stage of the design. Four Corner models were used for the final simulation to save time. NanoTime was used for the Static Timing Analysis. Hercules for DRC and LVS and StarRC for parasitic extraction. Area and power were in consideration throughout the design.

  • Standard Cell Library in SYNOPSYS

    Designed standard cell library in Custom Designer(SYNOPSYS) for 32nm and 45nm Predictive Technology Model(PTM). Simulated basic gates and analyzed the waveforms in WaveViewer.This helped me to get experience in SYNOPSYS CAD tools.

    Tools: Synopsys CAD - Custom Designer and Waveviewer

  • ATPG for 16-bit ALU

    Automatic Test Pattern Generation(ATPG) for 16-bit ALU using synopsys Tetramax. Developed VHDL and verilog codes for 16-bit ALU and used it to find stuck-at-faults,undetected faults and fault coverage in design.

    Tool: Synopsys CAD: Tetramax

  • Implementation of 4 bank, 256k-bit 6T SRAM Single-port Memory Array in 32nm FreePDK technology.

    -

    Design and implementation of SRAM (2048*128bit = 256Kb) Macro using row circuitry and column circuitry, with critical path timing analysis, full chip DRC, LVS and parasitic extraction.

    Tools : Synopsys Custom designer.

  • Design of a full custom microprocessor using Hardware and Software components.

    -

    •Designed a full custom 5 stage pipelined processor in Cadence - Schematic and Layout.
    •Major optimization in terms of area, power and delay were achieved by various techniques like dynamic logic, power gating, clock gating, Flip Flop optimization and careful sizing.
    •Perl was used to automate the entire flow and solve the dependencies. Back end Perl scripting was done to verify the results.

    Tools: Cadence CAD - Virtuoso 6.1.5
    Scripting Language - Perl

Honors & Awards

  • International Gateway Scholarship

    Wright State University

Languages

  • English

    -

  • Hindi

    -

  • Gujarati

    -

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