Prudhvi Thota

Is VLSI Talent Acquisition still seen as a cost center in 2025? Let’s change that. Every chip company wants the best ASIC, SoC, and Firmware talent. But not every company treats hiring as a strategic function. Too often, I see: 🔸 Hiring plans driven by urgency—not roadmap alignment 🔸 Recruiters chasing unrealistic timelines without clear JD-to-skill mapping 🔸 Interviewers chosen by availability, not capability 🔸 Offers made before stakeholder calibration is complete But when hiring works—it changes everything: 💥 Execution speed 💥 Team morale 💥 Retention 💥 Tapeout timelines So why are TA leaders still fighting for a seat at the table? If 2025 is the year of GenAI and semiconductor resurgence— It must also be the year TA becomes a business partner, not a backend service. What I believe: ✅ Every headcount should tie back to silicon delivery KPIs ✅ TA should sit with engineering leadership—not behind them ✅ Interviews should be structured like design reviews: consistent, data-backed, and outcome-driven Talent drives silicon. TA should drive strategy. If you're in TA, HR, or leadership in the VLSI space—what’s still holding us back from making this shift? Let’s start the conversation. 💬 #VLSI #Semiconductor #TalentAcquisition #HiringStrategy #Leadership #GenAI #TapeoutSuccess #RecruitingReimagined

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The future of SoC verification is here... Calibre's 2nd-gen Verilog-to-LVS achieves up to 4X faster translation and 92% less memory use for SoC signoff. Get a look at the architecture powering advanced verification results in this paper available here

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Hiring patterns changed. RAM prices explained. Hiring strategy across semiconductor companies has quietly shifted. 1. Less generic VLSI hiring 2. More demand for HBM & memory architecture experts 3. High-speed interfaces & advanced packaging 4. Bandwidth, power, and performance specialists That was the first signal. Then came my deductions AI doesn’t just need compute — it needs memory bandwidth. So memory companies shifted capacity from commercial DRAM to HBM for data centers and AI accelerators. What followed was inevitable: Less commercial RAM supply Same demand Higher prices everywhere This isn’t inflation. This is AI-driven prioritization. Your laptop RAM is now competing with AI data centers. And AI always wins. Strategic shift by memory vendors Slowing consumer & commercial DRAM Aggressively pushing HBM for AI & data centers Fewer wafers for PCs, phones, laptops More capacity reserved for high-margin HBM stacks Result? Even regular RAM feels expensive. Hiring patterns tell the future before prices do. Watching how the HBM ecosystem evolves across memory, foundry, and AI platforms. SK hynix / Samsung Electronics / Micron Technology / NVIDIA / AMD / Intel Corporation / TSMC / Amkor Technology, Inc. / ASE Global 💬 Curious to hear from memory, SoC, and system architects — Is HBM the biggest silent disruptor of this decade?

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There are multiple reasons why Verification is performed through SystemVerilog / UVM instead of Verilog. But among them, one of the prime reasons is that, Verilog used as a Static testbench and SV used in Dynamic testbenches that is based on OOP concept. There are range of concepts that are required to understand OOP and some of them are noted below: [1] What is Class and Object? Difference between handle and Object. [2] How memory allocation and deallocation is performed in Class. Difference b/w C pointer and SV object handle. [3] What is the use of constructor and how does constructor chaining is achieved. [4] How accidental overriding of base class methods are avoided. [5] Difference between Shallow copy and Deep copy. What are the things can be copied in Shallow Copy. [6] What is this construct in Class. What are Static methods in Class. [7] What is Inheritance. Difference between Multilevel and Multiple Inheritance. How does Data hiding property in Class is achieved. [8] How does Class extension can be restricted so that no subclass can inherit a parent class. [9] Difference b/w Static and Dynamic Casting. Application of casting in subclass and Superclass. [10] How a Class can be made read only. What are Virtual methods in Class. [11] Concept of Polymorphism and Abstract Class. What is an Interface Class and what it is used for. [12] How scope resolution operator is useful in accessing the static variables in the class. [13] Use of parameterised classes and when it is used. Default value of class constructor and its purpose. [14] How does Class allows access to the object during automatic garbage collection and what method needs to be used during that time. [15] Interface class and how it helps in multiple inheritance. [16] Diamond problem and how to solve the issue. [17] Concept of composition and aggregation in class. What is a Singleton class. ******** [18] Different Design pattern in class: a. Builder Method Design Pattern b. Factory Method Pattern c. Singleton Pattern d. Observer Pattern e. Prototype Pattern ****** [19] Difference between static and dynamic casting. [20] Memory Management in OOP. Objects reachability - Strongly reachable and Weakly reachable. [21] Use of super keyword in a class. How to override members of class. [22] What are local and protected members of class. Use of static methods. #vlsi #asic #electricalengineering #semiconductorindustry

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VLSI is categorised into many different subfields but primarily into Frontend and Backend. Considering Frontend, there are certain roles that a RTL and a Verification engineer has to pursue through out one's career. Below are some of the specific roles: [1] RTL Design Engineer: Mostly deals with the HDL coding and designing of various modules, blocks using VHDL/Verilog/SV and to make sure the design is synthesizable. Also deals with CDC analysis, Safety modules, lint and superlint, power and area estimation, etc [2] IP/SOC Design Engineer: The role is same as discussed above, only difference is with the blocks and Modules. IP is a basic building block of the design and the role of IP designer is to code the functionality of the IP. The role of SOC designer is to check whether all the IP's are integrated and write the code for Top level design. [3] RTL Integration Engineer: They mostly deals with the integration of different blocks, interconnection of signals, porting of module. [4] IP/Subsystem Verification Engineer: a. UVM/OVM based Verification Environment creation for IP or a subsystem. b. Creating Verification and Test Plan, Assertion Plan c. Writing Testcases ( Directed, Random, Stress, Corner) in SV or UVM to verify the features. d. Coverage closure and Regression Management, debugging Testcases, Proper Verification, CDC Verification. [5] Formal Verification Engineer: Model Checking, Register Verification, Exhaustive verification of blocks, RTL Equivalence checks, Algorithmic and Arithmetic Verification, Connectivity checks. [6] Power Aware Verification(UPF): Power domain, level shifter, Voltage domain, Power gating, Power estimation. [7] Safety Verification: FMEDA analysis, Calculating Diagnostic Coverage, Fault Injection in Simulation and Emulation, Fault analysis, Calculating Fault metric. a. Single point Fault. b. Multi point Fault c. Latent Fault. ☆ Verification of Safety mechanism ( ECC, MECC, Parity, etc) [8] SOC Verification Engineer: a. Integrating multiple IP's b. Connectivity Checks. c. C based Testcases d. Booting Sequence. e. Data Path Verification. f. Processor Verification. #vlsi #asic #electricalengineering #engineering

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99% of silicon verification engineers I’ve worked with across high-performance teams had this one habit that made them stand out: → They never underestimated CDC issues. They always prioritized CDC verification early and often. In multi-clock designs, CDC bugs are silent killers. They don’t show up in functional simulations. But they do show up in silicon—when it’s too late. CDC verification trumps post-silicon debugging, every single time: 1. A clean CDC report > A clean simulation run Because simulation won’t catch metastability or data loss across domains. 2. One async FIFO test > Endless waveform reviews You’ll find glitches, data corruption, and missed handshakes in minutes. 3. “Let’s run CDC lint” > “Let’s wait for integration” Early CDC checks save weeks of rework and painful root cause analysis. 4. One-day CDC tool run > Month-long debug cycles Tools like SpyGlass, Questa CDC, or VC CDC give instant feedback on risky crossings. 5. Even a flagged false positive > A missed real bug Because every CDC warning is a chance to learn, align, and improve design intent. The best DV engineers get this: → CDC isn’t just a checklist item. It’s a mindset. It’s about designing with clarity, verifying with rigor, and preventing the silent bugs that cost millions. CDC issues don’t shout. They whisper. And the best engineers are the ones who listen early. Have you faced CDC issues in your verification? Do let me know what do you think and have you heard about it? Comment down 👇🏻👇🏻 Like, comment and follow Jatin Koshiya to see more content like this. #cdc #dv #asyncfifo #verification #hiring #usa #ushiring #vlsijobs #mentor #jatinkoshiya

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It's a common mistake M.Tech freshers make on their resumes: listing basic circuits like adders, flip-flops, and gates and similar smaller circuits as their projects. While these are foundational, they aren't considered full projects in the professional world. A real project should demonstrate how you apply these concepts to create a more complex system. Recruiters want to see that you can move beyond theory and build something tangible. A strong project shows your ability to integrate multiple components into a cohesive design, not just your knowledge of a single building block. For instance, instead of listing a "4-bit adder," showcase a "data path for a simple CPU," which uses adders along with other components in a functional system. Verilog Projects for a Single Person Here are five projects you can tackle alone to make your resume stand out: 1. Simple CPU/Processor: Design a basic 8-bit or 16-bit CPU. This shows a deep understanding of computer architecture and control logic. For curious people use this github link for exploring one sample project: https://lnkd.in/gwQjDkpN 2. VGA Controller: Create a module to interface with a monitor. This project proves your skills in handling timing, synchronization, and memory. 3. Digital Clock with Alarm: Go beyond a simple counter and design a complex Finite State Machine (FSM) to manage different modes and user inputs. 4. Data Encryption/Decryption System: Implement a simplified cryptographic algorithm to demonstrate your ability to handle complex, bit-level data manipulation. 5. Audio Processing Unit: Build a simple digital filter or equalizer. This project introduces you to digital signal processing (DSP) and real-time data handling. By choosing a project like one of these, you'll be able to demonstrate a well-rounded skill set that goes far beyond a basic theoretical understanding of digital circuits. Good luck! #Verilog #DigitalDesign #VLSI #MTech #Freshers #CareerAdvice

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#) Why Puzzles Matter in Technical Interviews When preparing for interviews in domains like VLSI, Embedded Systems, or other core engineering roles, having technical skills is just one part of the equation. Many companies also assess your logical reasoning and analytical thinking, often by throwing in unexpected puzzle-based questions during the process. Interviewers use them to assess how you approach unfamiliar challenges - something that’s very common in real engineering roles. - Practicing different types of puzzles can help sharpen your problem-solving skills and boost your confidence during interviews. - I’ve compiled a PDF resource that includes real puzzle questions asked in various company interviews - this is Part 2 of the series. - You can find Part 1 here: https://lnkd.in/gFcZ9ZPK Hope this helps someone preparing for interviews. Let me know if you've faced any tricky ones during your interviews. Credits: www.geeksforgeeks.org P.S. Credits to the respective owners for their valuable insights and data.

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𝐇𝐞𝐥𝐥𝐨 𝐕𝐋𝐒𝐈 𝐀𝐬𝐩𝐢𝐫𝐚𝐧𝐭𝐬 👋 One of my Seniors currently working at Marvell Technology recently shared some powerful insights on Resume Building especially for VLSI and semiconductor roles like RTL Design, Verification, and Physical Design. His advice was incredibly helpful for me, and I’m sharing it here for the benefit of all fellow aspirants preparing to break into the VLSI industry. 𝐓𝐢𝐩 𝟏: 𝐔𝐧𝐝𝐞𝐫𝐬𝐭𝐚𝐧𝐝 𝐘𝐨𝐮𝐫 𝐀𝐮𝐝𝐢𝐞𝐧𝐜𝐞 🎯 Your resume has two readers: 1. ATS (Applicant Tracking System) filters your resume based on keywords like "SystemVerilog", "UVM", "RTL", "CDC", etc. 2. Human Recruiter has only 6–10 seconds to decide whether to continue. ▪️Use correct keywords + clear structure 𝐓𝐢𝐩 𝟐: 𝐅𝐨𝐜𝐮𝐬 𝐨𝐧 𝐈𝐦𝐩𝐚𝐜𝐭, 𝐍𝐨𝐭 𝐉𝐮𝐬𝐭 𝐃𝐮𝐭𝐢𝐞𝐬 1. Tailor your resume for each job 🔹 Use exact keywords from the JD e.g., "Static Timing Analysis", "Clock Gating", "Linting", etc. 2. Quantify ❌ “Worked on UART” ▪️Designed UART in Verilog, achieving 1.2 Gbps with 15% area reduction” 3. Use STAR-based bullet points ▪️Format: Action + Task + Tool + Result E.g., “Verified AXI protocol using SystemVerilog & UVM, reducing protocol violations by 40%” 4. Highlight Tools & Tech ▪️Vivado, QuestaSim, VCS, Design Compiler, SpyGlass, etc. 𝐓𝐢𝐩 𝟑: 𝐒𝐭𝐫𝐮𝐜𝐭𝐮𝐫𝐞 & 𝐋𝐚𝐲𝐨𝐮𝐭 Use a clean, ATS-friendly template (no fancy fonts/tables) 📋 Key Sections: ▪️Contact Info + LinkedIn ▪️Summary (customized to job role) ▪️Technical Skills (Grouped by category) ▪️Projects (Tools + Result focused) ▪️Education (Include CGPA) ▪️Certifications (Maven, ChipEdge, NPTEL, etc.) Project Example: "AHB to APB Bridge: Designed in Verilog, Verified using UVM in QuestaSim" Freshers: Stick to 1-page resume only 𝐓𝐢𝐩 𝟒: 𝐂𝐨𝐦𝐦𝐨𝐧 𝐌𝐢𝐬𝐭𝐚𝐤𝐞𝐬 𝐭𝐨 𝐀𝐯𝐨𝐢𝐝 ❌ Typos or grammar issues ❌ Irrelevant details (hobbies, religion, photo) ❌ Generic phrases like “responsible for…” ❌ Using “I” or “My” in bullet points ❌ Fake claims — you'll be asked in interviews! 𝐓𝐢𝐩 𝟓: 𝐅𝐢𝐧𝐚𝐥 𝐂𝐡𝐞𝐜𝐤𝐥𝐢𝐬𝐭 🔹 Print & proofread 🔹 Ask a mentor/senior for feedback 🔹 Be ready to explain everything you wrote 🤝Your resume is your first impression it must reflect clarity, impact, and technical strength. I hope these points help my fellow VLSI aspirants create resumes that not only pass ATS but also get shortlisted at top companies like Marvell, Qualcomm, Intel, AMD, and Synopsys.. 👉 Telegram Group: [https://lnkd.in/gUFtkEXt) 👉 Resume Format Samples: DM me if you need help with LaTeX or PDF version A small #cfbr (comment for better reach) 🙌 #vlsi #resume

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Breaking into VLSI Industry: A major chunk of my linkedIn messages are from bright, ambitious freshers who all ask the same thing: "How do I actually get into the VLSI Industry?" It's an awesome field, full of innovation, but getting your first foot in the door can feel pretty tough, especially right out of college. Let's be real, most of the top VLSI product companies tend to hire freshers directly from campus placements. If you're not coming from that pipeline, landing a role can be super difficult because of all the competition and their established campus relationships. But here's the good news: this isn't a dead end! There's definitely a smart, strategic way in, and I've seen many people successfully navigate it. Your VLSI Plan: 1. Build an Killer Portfolio: If direct campus access is tricky, your portfolio becomes your secret weapon. Don't just learn the theory, truly master Digital Electronics, SystemVerilog, and CMOS. Then, get your hands dirty! Build real projects – think of a simple RISC processor, a UART, anything you can design and implement. Use open-source tools, and make sure to show off your work on GitHub with clear explanations. Oh, and definitely pick up Python/TCL/Perl for scripting, it's a huge plus in VLSI. 2. Start Smart with Service Companies : This is often the easiest first step for freshers outside campus. VLSI service companies are more open to hiring new talent. Now, the pay might not be as high as a product company right away, but honestly, don't let that stop you! See this as an intensive learning boot camp. You'll get invaluable hands-on time with industry tools, various design flows, and real projects. 3. Let Experience Open Product Company Doors Once you've got about 1.5 to 3 years of solid, relevant experience under your belt from a service company, things change dramatically. You're no longer just a "fresher." Product companies actively seek experienced pros from the open market. Your proven skills and practical knowledge become super valuable, opening up a whole new world of roles you might not have been able to access initially. It's a journey that takes persistence and a smart approach, but trust me, a career in VLSI is absolutely within your reach! What are your thoughts on this strategy, or what's your biggest hurdle right now? Let's chat in the comments! Explore open-source EDA tools like: Icarus Verilog (for simulation): https://lnkd.in/grcdTvjQ Yosys (for synthesis): https://yosyshq.net/yosys/ Magic VLSI (for layout): https://lnkd.in/gd8VxkK7 Check out online platforms like EDA Playground for browser-based HDL simulation: https://lnkd.in/gJjzvAVj Look for project ideas and existing repositories on GitHub's VLSI topics : https://lnkd.in/gxf43z88 #VLSI #Semiconductor #CareerAdvice #Freshers #Engineering #DigitalDesign #Hardware #TechJobs #CareerPath #ExperienceMatters #OpenMarketHiring #India #Bengaluru

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I have been hearing from multiple hiring managers at semiconductor companies that what they look for in senior engineers is starting to change: The "most wanted" engineers today don’t fit perfectly into “hardware” or “software.” They are "hybrids". People who understand chip design and materials, but also know how software, AI models, and data interact with that hardware. Some will say, “that’s nothing new, hardware and software have always worked together.” Of course that is true, but the two areas are much more linked now I am starting to see. It’s not just about firmware anymore. So are chip designers starting to use AI tools to help design chips automatically. For example, using machine learning to optimise chip layouts or reduce power consumption. Big EDA vendors (Synopsys, Cadence) are adding AI capabilities to their tools. They use machine learning to speed up or improve tasks like verification, layout, power/performance/area tradeoffs, and error checking. DeepMind has developed a reinforcement-learning based system that generates chip layouts. The system can design layouts in hours that would normally take weeks. Their layouts have been used (or claimed to be used) in Google’s TPU chips. An other example: System engineers are designing hardware architectures (how the chip is structured) based on how AI models perform. This basically means the hardware is being built to match what AI models need. The integration is now at the core of how products are built. You can see this across the industry: * Nvidia blends hardware and AI expertise in the same teams. * ASML hires engineers who combine optics with data analytics. * Smaller design houses want verification engineers who can script and use AI tools. McKinsey projects the semiconductor industry will need over a million additional skilled workers by 2030, many in roles that blend hardware and software. But many companies still hire as if these disciplines were separate. From my conversations with industry experts, it’s clear that the next generation of AI-enabled chips will depend on teams who understand both sides. With that in mind, if you’re hiring, it might be time to rethink what makes someone qualified. I always suggest to look for curiosity, adaptability, and engineers who’ve worked across layers. Even if their background isn’t a perfect match. From my point of view, these hybrid engineers will make future products possible.

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Chip engineers feel in a rut after almost a decade on the job. Here's an actionable plan to get out of it. 👇🏽 First, why engineers feel stuck: → You do a tiny task in a huge flow. → When impact is unclear, motivation drops and you feel replaceable. The cycle is common: → Early excitement, then sameness, then burnout risk. → Promotions rarely solve the core issue. Apply a three-step plan: → Identify your career phase → Identify your personal engineer archetype → Run focused learning sprints. How to learn effectively? → Pick one adjacent skill (sub-field of EE, a programming language, etc). → Use what companies offer: tools, experts, tuition support. → Run a 6-week sprint: 3 hours/week, one mentor chat/week, one demo. → Request a 10–20% trial assignment to apply the skill. → Ship proof: a design note, a small block, or a script in production. How you benefit: → You build a rare skill mix, restore meaning, and open doors. → All without risky job-hopping. Read the article below for the complete blueprint: https://lnkd.in/g-BCwBiY ✍🏽 Subscribe: viksnewsletter.com 🔔 Follow me on LinkedIn for more ♻️ Repost if you find it helpful

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TA’s Thoughts on VLSI Recruitment 👇 I’ve observed an encouraging trend—more students are showing strong interest in chip design, verification, and physical design, and the industry is responding with growing opportunities. However, VLSI recruitment still demands a unique blend of: 🔹 Strong fundamentals in digital electronics and CMOS concepts 🔹 Hands-on proficiency with EDA tools and real project exposure 🔹 Problem-solving ability that goes beyond coursework 🔹 Consistency in building skills over time, not just during placements For students preparing to enter the semiconductor industry, my biggest takeaway is this: VLSI rewards depth, patience, and curiosity. If you invest time in understanding the “why” behind circuits, mastering tools, and building real projects, opportunities will follow. To recruiters and companies investing in young talent—thank you for supporting the next wave of semiconductor engineers. The enthusiasm among learners today is real, and with the right guidance, they are ready to contribute. Here’s to a stronger, innovation-driven VLSI ecosystem! �� #VLSI #Semiconductors #ChipDesign #EDA #Recruitment #Engineering

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*** Changing Role of Verification Engineers in a Chiplet World *** In a monolithic SoC world, a verification engineer’s job was mostly: o Ensuring functional correctness of individual IP blocks. o Running full-chip verification across a single die. o Debugging issues inside the same physical domain. But in a chiplet-based SoC, the role expands: o Understanding inter-chiplet protocols and system-wide behavior. o Modeling interactions across dies, not just within a single die. o Debugging failures where the root cause might be in the package, not just the chiplets themselves. Chiplet-based SoCs blur the lines between: o Digital and physical verification—since interconnect and package-level effects are inseparable. o Pre-silicon and post-silicon validation—because real-world behavior isn’t always captured in traditional simulations. o Design and verification responsibilities—since partitioning choices impact how easily a system can be tested. Verification is no longer just about "checking correctness"—it’s about understanding the full system at every level. How do we train the next generation of verification engineers for this shift?

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