Muhammad Younis

Cadence and NVIDIA have achieved hardware-accelerated dynamic power analysis for billion-gate AI designs, running billions of cycles in just hours with up to 97% accuracy. Together, NVIDIA's accelerated computing expertise and Cadence's EDA expertise are advancing power profiling to help make accelerated computing platforms more efficient.

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🚀 Socionext Breaks New Ground with 3DIC & 5.5D Packaging Socionext has officially taped out a next-gen SoC using TSMC’s SoIC-X 3D stacking—combining N3 compute and N5 I/O dies in a face-to-face (F2F) configuration. This milestone slashes latency, boosts bandwidth, and cuts power consumption, redefining what's possible in consumer, AI, and HPC applications. With support for chiplets, 2.5D, 3D, and now 5.5D packaging, Socionext is leading the charge in heterogeneous integration—bringing together multiple tech nodes and functions in a single, high-density package. 🔧 Vertical stacking. ⚡ Lower power. 📦 Smaller footprint. 💡 Limitless potential. #Semiconductors #3DIC #SoC #Innovation #Socionext #TSMC #AI #HPC #ChipDesign #TechLeadership #Hiring #Semiconductorhiring #ASIC #Marketing #TPM #Technicalprogrammanager(s) #SFBAYAREAJobs

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Silicon Labs just introduced Simplicity SDK for Zephyr RTOS, a fully supported Zephyr-based SDK designed for our low-power wireless platforms.    This gives developers the flexibility of Zephyr with the quality, validation, and long-term support required for production applications.    ➡️ Full details in the blog:

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the Intel Corporation is laying off hundreds of engineers in California, including chip designers and architects, while shutting down its automotive chip division to reduce costs and focus on core operations. The company will eliminate around 107 jobs at its Santa Clara headquarters starting July 15. These include engineers, architects, and managers working on CPU, GPU, and cloud products. Affected employees will receive notice periods and severance packages. Intel is also shutting down its automotive chip division, mainly based in Germany. The team, once focused on software-defined vehicle platforms, is being disbanded to sharpen Intel’s focus on client and data center products. Tan has emphasized flattening management and prioritizing efficiency. He criticized a culture where leadership was measured by team size and announced that future success will be judged by impact, not headcount. Intel is also outsourcing parts of its marketing to Accenture, using AI-driven solutions. For a deeper understanding of the latest semiconductor technologies, check out my new book, Semiconductor for All. Get your copy now on Amazon Kindle! https://lnkd.in/gzVV2fJm , For more updates and insights on AI and semiconductor, check out my blog, https://lnkd.in/gUmGrQh4 #semiconductor #ai #chips #manufacturing #semiconductorforall

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Almost exactly 3 years ago I was privileged to stand on stage in Santa Clara and announce the first wave of AI for verification. Today we make probably the most exciting announcement since then! Really excited to work with the ChipStack team as we define and develop Agentic AI for IC development together! ~~ We’re excited to announce that ChipStack, a pioneer in agentic AI for chip design and verification, is joining Cadence. ChipStack’s generative AI-driven platform helps accelerate design and verification workflows through deep design understanding, intelligent test planning, test generation, and AI-assisted debugging. Why this matters for our customers: ✅ Accelerated Verification – Move from weeks to days for front end IC design. ✅ AI-Powered Productivity – Scale without proportional headcount. ✅ Unified Flow – ChipStack’s generative AI agents will integrate seamlessly into Cadence’s Agentic AI and EDA solutions. ChipStack brings deep expertise in AI-driven design understanding, intelligent test planning, and AI-assisted debugging—strengthening our commitment to innovation and time-to-market acceleration. 👉 Read blog: https://ow.ly/NX2E50XpxZI #ChipStack #AI #Semiconductor #Design #Verification

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𝗧𝗼 𝗘𝘃𝗲𝗿𝘆𝗼𝗻𝗲 𝗪𝗵𝗼 𝗕𝘂𝗶𝗹𝗱𝘀 𝗦𝗶𝗹𝗶𝗰𝗼𝗻 ➖ "𝗖𝗵𝗶𝗽 𝗪𝗮𝗿" 𝗜𝘀 𝘁𝗵𝗲 𝗦𝘁𝗼𝗿𝘆 𝗬𝗼𝘂 𝗖𝗮𝗻’𝘁 𝗔𝗳𝗳𝗼𝗿𝗱 𝘁𝗼 𝗠𝗶𝘀𝘀 I just finished Chris Miller’s Chip War, and it hit differently when you’ve spent years chasing timing closure, debugging DRCs, or optimizing for PPA. We often see our work as purely technical, but this book reframes it entirely. It reminds us that we’re not just designing circuits; we’re building the foundation of global power. 🌍 𝗦𝗶𝗹𝗶𝗰𝗼𝗻 𝗧𝗵𝗲 𝗡𝗲𝘄 𝗢𝗶𝗹 𝗼𝗳 𝘁𝗵𝗲 𝟮𝟭𝘀𝘁 𝗖𝗲𝗻𝘁𝘂𝗿𝘆 In a world increasingly reliant on technology, the importance of semiconductors cannot be overstated. Every smartphone, car, satellite, and defense system depends on these tiny pieces of silicon the invisible engines driving our digital age. After diving deep into Chris Miller's "Chip War," I've come to realize: whoever controls chip manufacturing controls the future. 𝗧𝗵𝗲 𝗠𝗼𝘀𝘁 𝗣𝗼𝘄𝗲𝗿𝗳𝘂𝗹 𝗣𝗮𝗿𝘁𝗻𝗲𝗿𝘀𝗵𝗶𝗽 𝗬𝗼𝘂'𝘃𝗲 𝗡𝗲𝘃𝗲𝗿 𝗛𝗲𝗮𝗿𝗱 𝗢𝗳 Two companies. Two countries (Netherlands & Taiwan). One irreplaceable partnership. Without ASML's $350 million EUV lithography machines the most complex devices ever built advanced chips simply cannot exist. Only one company manufactures them. Without TSMC's manufacturing mastery, those machines are useless. Only one company can turn silicon into 3nm miracles at scale. Here's the reality: Every AI breakthrough, every smartphone, every advanced weapon system passes through these two companies. Not Google. Not Apple. Not even America or China can bypass them. 90%+ of the world’s advanced logic chips (<7nm) come from a single company on a single island. the quiet powerhouse that fabricates world’s most advanced chips. Whether your design’s at 5nm, 3nm, or the upcoming 2nm GAA odds are, it’s going to TSMC. 𝗧𝗵𝗲 𝗜𝗻𝗱𝗶𝗮 𝗔𝗻𝗴𝗹𝗲 India’s story feels different this time: 𝗙𝗮𝗯𝘀 𝗮𝗿𝗲 𝗰𝗼𝗺𝗶𝗻𝗴 (Micron ATMP, Tower partnership, Tata proposals) 𝗗𝗲𝘀𝗶𝗴𝗻 𝗲𝗰𝗼𝘀𝘆𝘀𝘁𝗲𝗺 is already World Class 𝗧𝗮𝗹𝗲𝗻𝘁 𝗽𝗶𝗽𝗲𝗹𝗶𝗻𝗲 is deep we just need manufacturing scale This could redefine local tape outs, reduce timezone bottlenecks, and open global opportunities from Indian soil. India's immediate success is not about competing with TSMC at the 2nm edge. It is about establishing resilient domestic capacity in crucial mature and specialty nodes for automotive, power, communications and industry automation. which currently accounts for the bulk of India’s import demand while simultaneously investing heavily in the R&D and talent needed to close the advanced node gap over the next decade. 💭 I’d like to hear your thoughts. #ChipWar #SemiconductorIndustry #VLSI #TechGeopolitics #SemiconIndia #SiliconPower #ChipDesign #FutureOfTech

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At Hot Chips Symposium 2025, one theme was clear: memory is shaping the future of AI. Bandwidth, capacity and efficiency determine how far compute can go. And, that’s why Marvell is leaning into innovations like dense 2nm SRAM, custom HBM architectures and high-capacity DDR expansion. Each layer is a step toward unlocking the scale AI models demand. Access this article to learn more about what the company is doing to ready the industry for excellence: https://mrvl.co/4lW2Zqn

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In my journey, I’ve seen how Physical Design engineers save a tape-out, how Analog layout experts quietly ensure performance, how DFT specialists catch what could cost millions post-silicon, and how Verification teams act as the last line of defense. Every discipline—Design, PD, Analog, Memory, Verification—carries the weight of the final chip. #Semiconductors #VLSI #Leadership #PhysicalDesign #Analog #MemoryDesign #TalentAcquisition #FutureOfWork

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Processor Classifications: --------------------------- Ever feel overwhelmed by the alphabet soup of processors? 🤯 ARM, x86, RISC-V, Harvard, von Neumann, CISC, RISC, MCU, MPU... it's a lot! To make sense of it all, I recently mapped out the entire processor landscape. Here’s a visual guide that breaks down processors by: 🔹 Instruction Set (ISA): From the dominant x86 in your laptop to the power-efficient ARM in your phone and the open-source promise of RISC-V. 🔹 Memory Architecture: The classic von Neumann vs. the high-performance Harvard. 🔹 Execution Model: The sequential world of SISD vs. the parallel power of SIMD, MIMD, and GPUs. 🔹 Core Purpose: Microcontrollers (MCUs) vs. Microprocessors (MPUs) – knowing which to use is half the battle. But it doesn't stop at theory! The mindmap dives into the real-world ecosystems, connecting these classifications to the powerhouse families from: STMicroelectronics (STM32) Microchip (PIC, AVR) Texas Instruments (MSP430, Sitara) Infineon (XMC, AURIX) NXP (LPC, Kinetis, i.MX) Renesas (RA, RX) Silicon Labs (EFM32) ESP32 and Raspberry Pi RP2040 Whether you're an engineer choosing the right chip for your next project, a student trying to connect the dots, or just tech-curious, this map is for you. Check out the interactive mindmap here: https://lnkd.in/gc_uHGEt The goal? To have a single reference that connects fundamental concepts to the actual chips we use every day. What’s your go-to processor family for your projects, and why? Let’s discuss in the comments! 👇 #EmbeddedSystems #Microcontrollers #Microprocessors #Semiconductors #Hardware #Engineering #Technology #ARM #RISC_V #STMicroelectronics #Microchip #TexasInstruments #Electronics #IoT #Innovation

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Excited to share Silicon Labs' latest Simplicity SDK release. SiSDK 2025.12.0 delivers advancements in performance, power efficiency, multiprotocol support, and tooling, strengthening the platform for next-gen IoT development. Highlights span Bluetooth, Matter, embedded AI, security, and SDK architecture evolution. Find all the details here: https://lnkd.in/gujEajhK

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The rapid growth of AI computing is transforming data centers. NVIDIA is leading the shift to 800 VDC architectures and is teaming up with ADI to provide innovative power solutions that help to deliver safety and efficiency. By working together, we're helping to enable the future of AI by powering smarter, faster, and more resilient data centers. Read the full announcement here:

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