John W. Orr

Are Small-Capacity eMMCs on the Brink of Extinction? Major NAND manufacturers are pulling the plug on small-capacity storage: 4GB eMMC 8GB eMMC SSDs under 32GB Low-density modules Why? Economics. But this leaves industrial, medical, and automotive applications in a tough spot. Think about it: ✅ Boot drives (~1-2GB) ✅ PLC controllers (~500MB-1.5GB) ✅ Medical device firmware (~1-3GB) ✅ HMI/operator interfaces (~1GB) These aren’t optional—they’re mission-critical. Yet they’re becoming “legacy” overnight, creating a supply crunch for systems that can’t be redesigned easily. 👉 Are you tracking EOL notices for your small-capacity storage? 👉 Do you have enough stock to keep production running? Don’t wait until it’s too late. Secure your supply now: https://lnkd.in/gfCYMdBP Send Your RFQ! We ADD Value! Learn more: ktts.us Request for quote: https://lnkd.in/gAWMHAqh Book a call: https://lnkd.in/gQAB2qZM Subscribe for the latest updates: https://lnkd.in/gua6gy9k #EmbeddedSystems #IndustrialAutomation #MedicalDevices #AutomotiveTech #eMMC #FlashStorage #SupplyChainRisk #LegacySystems #TechSolutions #KTTechnicalSolutions

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𝗠𝗼𝘀𝘁 𝘀𝗰𝗵𝗲𝗺𝗮𝘁𝗶𝗰 𝗲𝗿𝗿𝗼𝗿𝘀 𝗱𝗼𝗻’𝘁 𝗵𝗮𝗽𝗽𝗲𝗻 𝗯𝗲𝗰𝗮𝘂𝘀𝗲 𝗲𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝘀 𝗱𝗼𝗻’𝘁 𝗸𝗻𝗼𝘄 𝗲𝗹𝗲𝗰𝘁𝗿𝗼𝗻𝗶𝗰𝘀. They happen because the schematic wasn’t clear. If your schematic is hard to read, it will be hard to debug and review. 𝗛𝗲𝗿𝗲 𝗮𝗿𝗲 𝟯 𝗽𝗿𝗮𝗰𝘁𝗶𝗰𝗮𝗹 𝘄𝗮𝘆𝘀 𝘁𝗼 𝗱𝗿𝗮𝘄 𝘀𝗰𝗵𝗲𝗺𝗮𝘁𝗶𝗰𝘀 𝘁𝗵𝗲 𝗿𝗶𝗴𝗵𝘁 𝘄𝗮𝘆 𝗳𝗼𝗿 𝗯𝗲𝘁𝘁𝗲𝗿 𝗰𝗹𝗮𝗿𝗶𝘁𝘆: 𝟭. 𝗙𝗼𝗹𝗹𝗼𝘄 𝘀𝗶𝗴𝗻𝗮𝗹 𝗳𝗹𝗼𝘄, 𝗻𝗼𝘁 𝗰𝗼𝗺𝗽𝗼𝗻𝗲𝗻𝘁 𝗼𝗿𝗱𝗲𝗿   Arrange your schematic so signals flow logically (left --> right or top --> bottom). 𝟮. 𝗚𝗿𝗼𝘂𝗽 𝗿𝗲𝗹𝗮𝘁𝗲𝗱 𝗰𝗼𝗺𝗽𝗼𝗻𝗲𝗻𝘁𝘀 𝗶𝗻𝘁𝗼 𝗳𝘂𝗻𝗰𝘁𝗶𝗼𝗻𝗮𝗹 𝗯𝗹𝗼𝗰𝗸𝘀   Don’t scatter parts everywhere.   MCU + decoupling caps = one block   Regulator + passives = one block 𝟯. 𝗨𝘀𝗲 𝗻𝗲𝘁 𝗹𝗮𝗯𝗲𝗹𝘀 𝗶𝗻𝘀𝘁𝗲𝗮𝗱 𝗼𝗳 𝗹𝗼𝗻𝗴 𝗰𝗿𝗼𝘀𝘀𝗶𝗻𝗴 𝘄𝗶𝗿𝗲𝘀   Long wires crossing the page reduce clarity and increase mistakes.   Use meaningful net names like:   VCC_3V3, SPI_MOSI, UART_TX 𝗔 𝗰𝗹𝗲𝗮𝗿 𝘀𝗰𝗵𝗲𝗺𝗮𝘁𝗶𝗰 𝘀𝗮𝘃𝗲𝘀 𝘁𝗶𝗺𝗲, 𝗽𝗿𝗲𝘃𝗲𝗻𝘁𝘀 𝗹𝗮𝘆𝗼𝘂𝘁 𝗺𝗶𝘀𝘁𝗮𝗸𝗲𝘀, 𝗮𝗻𝗱 𝗺𝗮𝗸𝗲𝘀 𝗰𝗼𝗹𝗹𝗮𝗯𝗼𝗿𝗮𝘁𝗶𝗼𝗻 𝗲𝗮𝘀𝗶𝗲𝗿. If you’re building a real product and want help turning your idea into a manufacturable electronic design, from schematic to PCB to production, reach out for product design support. #hardware #electronics #schematics PCB Mentor

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Are we barking up the wrong tree? Rethinking the U.S. domestic PCB/advanced packaging/chip situation: Where is the need most critical with the least support? Certainly not in chip making foundries with the hundreds of billions of dollars committed. I venture to say that it is not the packaging of the Chips. The billions committed by the U.S. based consortium (headed by Resonac with KLA, Azimuth, Kulicke & Soffa, TOK, Toppan, Towa, Ulvac, Namics, 3M and others), Amkor’s Arizona OSAT commitment, SK Hynix in Indiana, TSMC’s Arizona plans and activities for 2 in-house packaging operations, and others seem to verify that. What’s missing? The PCBs including organic substrates and UHDI circuitry needed to mount and use the packaged ICs. Other than commitments and actions by a handful of companies there is a woeful U.S. shortage of incentive, investment and activity to produce the PCBs needed to mount the packages that will be made in America for defense, medical equipment, AI data centers and other critical needs. The focus must now be on PCB fabrication and its supply chain of materials, specialty chemicals and manufacturing equipment. This must be supported by the OEMs that will use and benefit from the finished electronic devices. It needs government support and incentives to encourage investment by the private sector. What do you think? As the PCBAA (Printed Circuit Board association of America) is wont to say, “Chips don’t float!”

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7 best practices for designing #RF vias 1️⃣ Design the via to maintain low return loss at the input, especially when dealing with wide bandwidths extending into the GHz range. 2️⃣ Ensure the presence of vias does not negatively impact the insertion loss. While insertion loss is not usually the focal point for vias, it is still a critical factor. 3️⃣ Maintain a minimum spacing of  λ/10 between the ground vias. For instance, at 2.4 GHz, the clearance should be 6 mm. 4️⃣ Place ground-connected vias near the PCB edges to reduce RF losses through the laminate. The EMFs are less confined near the edges. However, avoid placing them too close to the edge to prevent mechanical issues. 5️⃣ For mmWave PCBs, implement a via fence around grounded coplanar waveguides to enhance high-frequency isolation. This technique also suppresses frequencies below a cut-off and prevents mmWave interference with other signals. 6️⃣ Avoid return or stitching vias for slow-speed signals with rise times higher than 20 ns (e.g., GPIOs, I2C, and control signals) because such signals are less sensitive to impedance discontinuities. 7️⃣ Prioritize transition methods and the implementation of return paths (e.g., stitching vias) for higher-frequency signals or those with fast rise times to minimize radiation or crosstalk. 👇Check the link in the comments for more details. --> Repost for better reach. #rfengineers #radiofrequencydesigners #hardwareengieers #electricalengineering

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Many hardware teams don’t need “more headcount.” They need senior capacity in bursts. Because the workload isn’t steady, it comes in spikes: architecture / power tree decisions high-risk PCB reviews (PI/EMI/DFM) bring-up + root cause when something’s flaky manufacturing pack + test strategy before a build supplier/BOM shocks (alternates, EOL, cost-down without breaking stuff) Hiring a full-time senior for every spike is expensive and slow. Pushing your core team through every spike is how you end up with extra spins, late nights, and a lot of “it worked yesterday” The pattern that seems to work best: keep a lean core team + pull in senior help for the spikes. For ID studios and EMS partners, this is also a clean way to support clients without expanding permanently: bring the “adult supervision” when it matters, then step out of the way. Where do you feel the spikes the most: architecture, bring-up, DFM/test, or “BOM chaos”?

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Altium or KiCad—when does “free” start costing you? “Version 9… just kidding! 😏” That jab in our chat with Zach Peterson got a laugh—but it hits on something real. (Oh Sean 🤦‍♂️ ) Everyone starts somewhere. KiCad is a great launchpad. But once you’re designing for production, scalability, or tight timelines, it’s time to level up. Here’s where pro tools like Altium start pulling their weight: ✅ Real-time supply chain integration – no last-minute BOM surprises ✅ Constraint-driven routing – signal integrity + DFM in one pass ✅ 3D clearance + MCAD sync – shave weeks off electro-mechanical handoffs ✅ Centralized libraries + vaults – one golden component, no revision chaos Free tools get you started. Pro tools help you ship, scale, and stay sane. 🎥 60-second clip below—Zach keeps it funny and factual. #PCBDesign #Altium #KiCad #EDAtools #HardwareDesign #DesignForManufacturing #ElectronicsEngineering

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CAN Transceiver: Core Principles and PCB Layout in One Page 🚀 If you've designed CAN buses long enough, you've probably learned one thing the hard way: most CAN issues are layout problems, not protocol problems. Here's a practical breakdown of CAN transceiver PCB layout, based on real bring-up, EMC, and manufacturing feedback. 🔴 Common-Mode Choke ◾ Placement matters most Place the common-mode choke as close as possible to the CAN transceiver CAN_H / CAN_L pins (ideally < 5 mm). Too far away, and common-mode noise is already on the bus. ◾ Orientation is not optional Follow the datasheet reference design. If in doubt, copy the manufacturer layout exactly. A simple trick: mark signal flow direction on the schematic to avoid layout mistakes. 🔴 Power Decoupling ◾ Local decoupling is mandatory Use a 0.1 µF ceramic (high-frequency) plus a 10 µF bulk capacitor at each VCC pin. Even a few millimeters of extra trace length reduces effectiveness. ◾ One pin, one capacitor Especially critical in automotive and industrial designs with noisy supply rails. 🔴 ESD Protection ◾ Place ESD diodes at the connector The protection device must sit closer to the CAN connector than the transceiver. Otherwise, the ESD pulse reaches the IC first. ◾ Short, wide ground return Use a direct, low-impedance path to the ground plane. Long routes defeat protection. 🔴 Termination resistor ◾ 120 Ω means 120 Ω This matches the CAN bus characteristic impedance. Small deviations often show up as ringing or marginal communication. ◾ Only at the ends of the bus Two-node system: one at each end. Multi-node system: only the two far ends. Never in the middle. ◾ Check the datasheet Some transceivers integrate internal termination. 🟥 Routing rules for CAN_H / CAN_L 1️⃣ Treat them as a true differential pair Tight length matching (< 5 mil), parallel routing, consistent spacing (3W rule). 2️⃣ Keep them away from aggressors Avoid long parallel runs with clocks or high-current power traces. A continuous reference plane underneath is essential. 3️⃣ Minimize vias Every via introduces an impedance discontinuity. If unavoidable, keep transitions symmetrical and avoid stubs. 📌 A DFM Note From a manufacturing perspective, CAN failures often trace back to details that look electrically fine on schematics: ◼️ Common-mode choke pads too small → tombstoning or skew during reflow ◼️ ESD diode ground vias too far away → ineffective protection despite correct parts ◼️ Termination resistor placed across split planes → impedance inconsistency after lamination ◼️ Differential pair spacing altered by copper pour or mask openings → unintended impedance shift ◼️ These are rarely caught in simulation — they show up during assembly, EMC testing, or field deployment. Good CAN designs are quiet, boring, and invisible. "Good design is buildable design." #CANBus #PCBDesign #HardwareDesign #EmbeddedSystems #AutomotiveElectronics #SignalIntegrity #EMI #DFM #Manufacturing #BoardBringUp

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*** Yield isn’t just about the wafer anymore. In chiplet systems, packaging contributes as much risk as fabrication. *** Chapter 8 of my book "Chiplet-based SoC Architecture" explains how assembly constraints quietly erode yield and what teams can do to catch issues earlier.​ ​ Now available on Amazon in hardcover, paperback, and Kindle.  Links in the comments. ​​

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📡 Load Pull Analysis with Modulated Signal Input and EVM Contours in Keysight ADS In modern RF and microwave design, optimizing power amplifier (PA) performance under realistic signal conditions is critical. Traditional load pull techniques using CW tones are insightful, but they fall short when it comes to predicting behavior under complex modulated signals. This is where modulated load pull and EVM contour analysis in Keysight Advanced Design System (ADS) come into play. 📈 Why EVM Contours Matter EVM contours provide a visual map of how modulation quality varies with load impedance. This helps: --Identify load regions that meet system-level EVM requirements. --Optimize matching networks for best linearity and spectral performance. --Accelerate design cycles by focusing on viable impedance zones. Check out below link in Keysight Knowledge Center and download the workspace: https://lnkd.in/gKZaXwTv (Courtesy: Andy Howard) P.S. : Many examples available to be explored in Knowledge Center.

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Most AI glasses projects don’t fail at architecture or algorithms. They fail much later — during PCBA. The schematics are clean. The layout passes DRC. The prototype boots. And then yield collapses. 🔍 Where PCBA breaks down in AI glasses 1) Fine-pitch BGA + ultra-small boards Minimal board area means tighter thermal gradients during reflow. Even small warpage shifts can cause intermittent opens or head-in-pillow defects. 2) Via-in-pad paste control Too much paste → shorts. Too little → voids and unstable joints. On wearable boards, the window is extremely narrow. 3) Double-sided reflow imbalance AI glasses boards are almost always double-sided. Component density on both sides makes profile tuning non-trivial. 4) AOI blind zones Large packages + compact layouts reduce optical visibility. Electrical issues hide until functional testing — or worse, in the field. 5) Functional testing comes too late By the time failures appear, rework options are limited by board size and component pitch. 🧩 The uncomfortable truth In wearable AI products, PCBA yield defines whether the product is manufacturable at all. Design gets the idea working. Assembly decides whether it can scale. That’s why for AI glasses, PCB and PCBA can’t be treated as separate steps — they must be engineered together from the start. If you’re building AI audio or camera glasses and preparing for volume, happy to exchange notes from the manufacturing side. 📩 lana@lzjpcb.com #AIGlasses #PCBA #HDI #WearableTech #AIHardware #Manufacturing #HardwareEngineering #Electronics #DFM #B2B

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