Jason Ding

There is a growing trend to insert application intelligence into network devices. Processors in this type of Application Oriented Networking (AON) devices are required to handle both packet-level network I/O intensive operations as well as XML message-level CPU intensive operations. In this paper, we investigate the performance effect of symmetric multi-processing (SMP) via (1) hardware multi-threading, (2) uni-processor to dual-processor architectures, and (3) single to dual and quad core… Show more

There is a growing trend to insert application intelligence into network devices. Processors in this type of Application Oriented Networking (AON) devices are required to handle both packet-level network I/O intensive operations as well as XML message-level CPU intensive operations. In this paper, we investigate the performance effect of symmetric multi-processing (SMP) via (1) hardware multi-threading, (2) uni-processor to dual-processor architectures, and (3) single to dual and quad core processing, on both packet-level and XML message-level traffic. We use AON systems based on Intel Xeon processors with hyperthreading, Pentium M based dual-core processors, and Intel's dual quad-core Xeon E5335 processors. We analyze and cross-examine the SMP effect from both high level performance as well as processor microarchitectural perspectives. The evaluation results will not only provide insight to microprocessor designers, but also help system architects of AON types of device to select the right processors. Show less

In this paper, we analyze virtual machine (VM) scalability on multi-core systems for compute-, memory-, and network I/O-intensive workloads. The VM scalability evaluation under these three workloads will help cloud users to understand the performance impact of underlying system and network architectures. We demonstrate that VMs on the state-of-the-art multi-core processor based systems scale as well as multiple threads on native SMP kernel for CPU and memory intensive workloads. Intra-VM… Show more

In this paper, we analyze virtual machine (VM) scalability on multi-core systems for compute-, memory-, and network I/O-intensive workloads. The VM scalability evaluation under these three workloads will help cloud users to understand the performance impact of underlying system and network architectures. We demonstrate that VMs on the state-of-the-art multi-core processor based systems scale as well as multiple threads on native SMP kernel for CPU and memory intensive workloads. Intra-VM communication of network I/O intensive TCP message workload has a lower overhead compared to multiple threads when VMs are pinned to specific cores. However, VM scalability is severely limited for such workloads for across-VM communication on a single host due to virtual bridges. For across local and wide area network communication, the network bandwidth is the limiting factor. Unlike previous studies that use workload mixes, we apply a single workload type at a time to clearly attribute VM scalability bottlenecks to system and network architectures or virtualization itself. Show less

L7-filter is a significant component in Linux's QoS framework that classifies network traffic based on application layer data. It enables subsequent distribution of network resources in respect to the priority of applications. Considerable research has been reported to deploy multi-core architectures for computationally intensive applications. Unfortunately, the proliferation of multi-core architectures has not helped fast packet processing due to: 1) the lack of efficient parallelism in legacy… Show more

L7-filter is a significant component in Linux's QoS framework that classifies network traffic based on application layer data. It enables subsequent distribution of network resources in respect to the priority of applications. Considerable research has been reported to deploy multi-core architectures for computationally intensive applications. Unfortunately, the proliferation of multi-core architectures has not helped fast packet processing due to: 1) the lack of efficient parallelism in legacy network programs, and 2) the non-trivial configuration for scalable utilization on multi-core servers. In this paper, we propose a highly scalable parallelized L7-filter system architecture with affinity-based scheduling on a multi-core server. We start with an analytical study of the system architecture based on an offline design. Similar to Receive Side Scaling (RSS) in the NIC, we develop a model to explore the connection level parallelism in L7-filter and propose an affinity-based scheduler to optimize system scalability. Performance results show that our optimized L7-filter has superior scalability over the naive multithreaded version. It improves system performance by about 50% when all the cores are deployed. Show less

Stream-based simultaneous XPath processing plays a critical role in service oriented networking, where the processing must scale well in terms of concurrent input streams and number of XPath queries. However, there are no benchmarks or evaluation methodology in existing literatures that benchmark stream-based XPath engines supporting simultaneous queries. In this paper, we describe a novel benchmarking methodology for evaluating XPath engines which handle simultaneous queries on streaming… Show more

Stream-based simultaneous XPath processing plays a critical role in service oriented networking, where the processing must scale well in terms of concurrent input streams and number of XPath queries. However, there are no benchmarks or evaluation methodology in existing literatures that benchmark stream-based XPath engines supporting simultaneous queries. In this paper, we describe a novel benchmarking methodology for evaluating XPath engines which handle simultaneous queries on streaming traffics. With structured data model, query model, and control model in our benchmark, we conduct well controlled experiments to assess and isolate various performance factors. We also demonstrate that our structured, quantified approach with wide data set coverage, enables accurate performance measurements, and easy bottleneck isolation of a real-world XPath engine implementation. Show less

Parsing is an expensive operation that can degrade XML processing performance. A survey of four representative XML parsing models, DOM, SAX, StAX, and VTD, reveals their suitability for different types of applications.

Cisco Systems application oriented networking (AON) product is an important network element towards building next generation service oriented intelligent information network (IIN). AON processes application-level content and moves far beyond a conventional content-aware Web switch. It creates a novel content delivery platform and allows more sophisticated load balancing schemes to be deployed in a switch among back-end servers to reduce user-perceived response time. In this paper, we… Show more

Cisco Systems application oriented networking (AON) product is an important network element towards building next generation service oriented intelligent information network (IIN). AON processes application-level content and moves far beyond a conventional content-aware Web switch. It creates a novel content delivery platform and allows more sophisticated load balancing schemes to be deployed in a switch among back-end servers to reduce user-perceived response time. In this paper, we investigate different scheduling techniques for an AON system to maximize overall throughput and minimize latency per message for a heterogeneous server cluster consisting of different application servers. Based on a thorough evaluation of the three existing load balancing algorithms of AON, we propose a novel message type based service adaptive scheduling algorithm that makes AON more efficient and more intelligent. Systematic performance measurements, analyses, and comparisons are conducted to demonstrate the superiority of our intelligent message scheduling technique. Show less

There is a growing trend to insert application intelligence into network devices. Processors in this type of application-oriented networking (AON) devices are required to handle both packet-level network I/O intensive operations as well as XML message-level CPU intensive operations. In this paper, we investigate performance effect of dual processing via (1) hyperthreading, (2) uni-processor to dual- processor, and (3) single-core to dual-core, on both packet-level and XML message-level traffic.… Show more

There is a growing trend to insert application intelligence into network devices. Processors in this type of application-oriented networking (AON) devices are required to handle both packet-level network I/O intensive operations as well as XML message-level CPU intensive operations. In this paper, we investigate performance effect of dual processing via (1) hyperthreading, (2) uni-processor to dual- processor, and (3) single-core to dual-core, on both packet-level and XML message-level traffic. We analyze and cross-examine the dual processing effect from both high-level performance as well as processor microarchitectural perspectives. We employ on-chip performance counters to measure cycles per instruction, cache misses, bus utilization, and branch miss predictions for this work. Our results show a significant improvement in dual-core Pentium M processor over Hyperthreaded Xeon processor for AON workload. These results will not only provide insight to processor designers, but also help architects of AON devices to select from alternative processors with restrictions to use one or two physical CPUs due to space and power consumption limitations. Show less

In this paper, we characterize the performance of several business and technical benchmarks on a Pentium Pro (1st-gen Xeon) processor based system. Key architectural data are collected using a performance monitoring counter tool and then are analyzed with the understanding of Pentium Pro microarchitecture and cache/memory organization. Results show that the Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out-of-order and… Show more

In this paper, we characterize the performance of several business and technical benchmarks on a Pentium Pro (1st-gen Xeon) processor based system. Key architectural data are collected using a performance monitoring counter tool and then are analyzed with the understanding of Pentium Pro microarchitecture and cache/memory organization. Results show that the Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out-of-order and speculative execution, and non-blocking cache and memory system. Its higher clock frequency also contributes to even higher performance Show less

Proposes an analysis technique for a class of Multistage Interconnection Networks (MIN's) that have finite buffers at their switch inputs and operate in a synchronous packet-switched mode. The authors examine the issue of clock period in design and analysis of synchronous MIN's and propose a model based on small clock periods. Then they analyze their "small cycle" design and compare the results with those obtained from the standard "big cycle" model that is currently used. The significant… Show more

Proposes an analysis technique for a class of Multistage Interconnection Networks (MIN's) that have finite buffers at their switch inputs and operate in a synchronous packet-switched mode. The authors examine the issue of clock period in design and analysis of synchronous MIN's and propose a model based on small clock periods. Then they analyze their "small cycle" design and compare the results with those obtained from the standard "big cycle" model that is currently used. The significant performance improvement of their model is shown based on various clock width, data width, and buffer length. Show less

In this paper, we propose an adaptive scan (AS) strategy for submesh allocation. The earlier frame sliding (FS) strategy allocates submeshes based on fixed orientations of incoming tasks. It also slides frames on mesh planes by fixed strides. Our AS allocation strategy differs from the FS strategy in the following two ways: (1) it does not fix the orientations of incoming tasks; (2) it scans on mesh planes adaptively. Experimental studies show that our AS strategy outperforms the FS strategy in… Show more

In this paper, we propose an adaptive scan (AS) strategy for submesh allocation. The earlier frame sliding (FS) strategy allocates submeshes based on fixed orientations of incoming tasks. It also slides frames on mesh planes by fixed strides. Our AS allocation strategy differs from the FS strategy in the following two ways: (1) it does not fix the orientations of incoming tasks; (2) it scans on mesh planes adaptively. Experimental studies show that our AS strategy outperforms the FS strategy in terms of external fragmentation, completion time, and processor utilization. Show less