Ben Mitchel

Are you puzzled about which battery will truly perform in your wireless device out in the real world? Remember, it's not just about the datasheet specs. You have to factor in manufacturing differences, verify actual performance, and determine how long your device will last under actual usage conditions. Dive into this article to learn how to assess batteries with precision, compare different suppliers, and steer clear of unexpected issues during testing: https://lnkd.in/eib8UcyE

1

🚨 Copper isn't dead. It’s moving closer to the chip. As AI data centers push toward 200G, 224G and eventually 448G electrical lanes, traditional PCB routing becomes a major bottleneck. Enter CPC — Co-Packaged Copper. 🔌 What is CPC? Traditional architecture: ASIC → BGA → PCB → connector → cable CPC changes the path: ASIC → package substrate → high-speed copper cable Instead of forcing high-speed signals through long PCB traces, CPC uses compact twinax / flyover copper assemblies connected directly to the package substrate. That dramatically reduces the electrical channel between the silicon and the cable. ⚡ Why does this matter? At 224G PAM4, every millimeter matters. Longer PCB traces mean: ❌ More insertion loss ❌ More reflections ❌ More crosstalk ❌ More equalization ❌ More power ❌ More signal-integrity challenges CPC attacks the problem at the physical layer: Shorter electrical path → lower loss → better signal integrity → lower power. And unlike optics, copper doesn't require optical engines, lasers or photodetectors. 🏗️ How is CPC manufactured? The interesting part is that this is not simply “a cable attached to a chip.” The process involves: 1️⃣ High-density package substrate design 2️⃣ High-speed I/O escape directly from the substrate 3️⃣ Precision connector / contact attachment 4️⃣ Twinax or flyover copper assembly 5️⃣ Controlled impedance routing 6️⃣ Mechanical retention and thermal integration 7️⃣ High-speed electrical characterization 8️⃣ BER / eye-diagram / SI validation Samtec, for example, has demonstrated 224G PAM4 CPC integrated on substrates as small as 95 × 95 mm. 🧠 Who is using / developing it? Some of the key players include: 🔹 Marvell Technology — 224G SerDes + CPC architectures 🔹 Broadcom — high-speed SerDes demonstrations 🔹 Samtec Inc — Si-Fly HD CPC 🔹 Molex — Impress co-packaged copper 🔹 Luxshare-Tech — CPC and long-reach copper solutions 🔹 BizLink Group — high-speed copper interconnects 🤖 Where does CPC fit? Think of the data center interconnect stack: Short reach → Copper CPC / DAC / AEC / ACC ⬇️ Longer reach → Optical Optical modules / CPO / Silicon Photonics CPC is particularly attractive for scale-up and intra-rack connectivity, where copper can still provide major advantages in cost, power and latency. 📦 And here's the semiconductor packaging implication: CPC makes the package substrate part of the networking architecture. The substrate now has to handle: → Extremely high I/O density → 200G/224G+ SerDes → Controlled impedance → Signal integrity → Mechanical interfaces → Thermal constraints So the boundary between: Chip design ↔ Packaging ↔ Networking is disappearing. ATPION

32

🚀 Think MOSFET gain is just “datasheet talk”? Most engineers underestimate how critical transconductance really is. Our calculator shows you the exact value based on drain current and effective voltage—no guesswork, just clarity. Perfect for anyone optimizing semiconductor performance or validating voltage gain in design cycles. Try it here 👉 https://ow.ly/Q80G50XxptJ #electronics #mosfet #semiconductors #electricalengineering #powerelectronics #engineeringtools

2

The semiconductor industry isn’t one industry. It’s 8 industries stacked on top of each other. And most people only ever see one. That’s why the semiconductor world feels so confusing from the outside. Different business models.   Different incentives.   Different bottlenecks. Here’s the simplest way to understand how it actually works 👇 1) Chip design (fabless)   These companies design chips but don’t manufacture them.   They create the architecture and rely on foundries to build it.  Top players: NVIDIA, Qualcomm, Broadcom, AMD, MediaTek 2) In-house chip designers   Their core business isn’t chips.   The silicon exists to power their own products or platforms.  Top players: Apple, Google, Amazon, Tesla, Microsoft 3) IP & design tools   The invisible layer.   Without these tools and IP blocks, nothing gets taped out.  Top players: Arm, Cadence, Synopsys 4) Foundries   They turn designs into silicon.   Extreme precision. Massive capital. Zero room for mistakes.  Top players: TSMC, Samsung Foundry, UMC, GlobalFoundries, SMIC 5) Equipment makers   They don’t make chips.   They make the machines that define what chips can be made.  Top players: ASML, Applied Materials, Lam Research, KLA 6) Materials & components   Wafers, substrates, chemicals, passives.   Unsexy — and absolutely critical.  Top players: Murata, TDK, Ibiden, Unimicron, Samsung Electro-Mechanics 7) Assembly & testing (OSAT)   Where chips are packaged, tested, and prepared for the real world.   This step decides yield, cost, and reliability.  Top players: ASE Group, Amkor, JCET 8) Integrated players (IDMs)   Design and manufacturing under one roof.   More control. More risk. More complexity.  Top players: Intel, Samsung, Micron, Texas Instruments, Infineon Final products (OEMs)   They don’t care how the chip was made.   They care that it works, ships on time, and hits cost targets. The key takeaway: No single company “builds a chip.” A chip is the result of a global relay race,   where every handoff matters. That’s why semiconductors are hard to scale,   slow to localize,   and impossible to simplify. Which layer of this stack do you think is the most misunderstood?

817

49 Comments

Memory Industry to Maintain Cautious CapEx in 2026, with Limited Impact on Bit Supply Growth, Says TrendForce Corp. TrendForce’s latest investigations reveal that despite higher ASPs boosting profitability across the #memory industry, capital spending on #DRAM and #NAND Flash is only anticipated to increase modestly in 2026. This limited #investment growth is unlikely to significantly affect bit output. Instead, the emphasis is shifting from capacity expansion to advancements such as process #technology upgrades, higher-layer stacking, hybrid bonding, and high-value products such as #HBM. In the DRAM sector, total capital expenditure is expected to reach US$53.7 billion in 2025 and rise to $61.3 billion in 2026, representing about 14% YoY growth. For #NANDFlash, spending is projected to rise from $21.1 billion in 2025 to $22.2 billion in 2026, a roughly 5% increase. A very big thank you again to TrendForce Corp. for the full article with more background and insights via the link below 🙏💡👇´ https://lnkd.in/eUngrwPA #semiconductorindustry #semiconductormanufacturing #tech #korea #usa #japan #singapore #taiwan #china #it #server #ai #computer #iot Samsung Semiconductor SK hynix Micron Technology Nanya Technology Winbond POWERCHIP TECHNOLOGY CORPORATION ChangXin Memory Technologies, Inc. KIOXIA Group Sandisk Yangtze Memory Technologies

80

3 Comments

A timely post from Jordan Mitchell, MILLIBEAM’s Head of RF PA development on our #GaN #RF #PA innovation. At MILLIBEAM, we are bringing high-performance and unparalleled reliability to mission-critical markets that have been relegated to an afterthought. #radars #defence #satcom

18