Lam Research

In 1998, SABRE® ECD pioneered the copper interconnect transition, while a major search engine entered the world — making 1998 a big year in tech. Let’s go back to the past. ⬇️

Careers change as you learn what you want to build and where you want to have impact. At Lam, we encourage and support that exploration. Process Engineer Rachel Nye de Castro shows what it looks like to ask questions, build new skills, and make a shift with managers who invest in your growth. https://bit.ly/3N19gWa

Flex your semiconductor knowledge with our Word(s) of the Week! Hint: It reduces capacitance, minimizes delay, and keeps performance high as chips continue to scale. Swipe to see if you guessed this week’s term correctly. 😉

The transition to 2nm technology represents a significant milestone for the semiconductor industry. As device complexity increases and design rules tighten, next generation architectures require new approaches to patterning, deposition, and etch to achieve the needed precision and performance. Learn more about how the industry is shifting to 2nm manufacturing, why transistor scaling continues to drive new process requirements, and how innovations in materials and integration support the shift to more advanced nodes. https://bit.ly/4rdcULx

As device scaling approaches atomic dimensions, materials engineering is taking on a more central role in semiconductor progress. This article from Semiconductor Engineering explores how thin-film dielectrics, conformal barriers, and atomic-scale interfaces are increasingly responsible for electrical behavior, reliability, and performance in AI-era architectures. It also explains why atomic-layer deposition, ALD, is becoming essential for creating precise stacks in both front-end and back-end (BEOL) structures as dimensions shrink and aspect ratios rise. https://bit.ly/4kQo5r7

As AI drives demand for higher bandwidth and capacity, memory roadmaps are stretching. Lam’s Aether® dry resist technology is emerging as a key patterning approach for DRAM scaling and for HBM (High Bandwidth Memory) stacks that use thousands of TSVs (Through Silicon Vias) to connect multiple layers. Curious to learn more about how dry resist supports vertical integration and complex interconnects? https://bit.ly/4tBFAQ6

DRAM works like a sticky note — it keeps data close to the processor, but if you don’t constantly refresh it, it falls away. 🔄 As AI and high-performance systems demand more bandwidth and greater efficiency, memory innovation must accelerate just as fast. DRAM is built for velocity, temporarily storing active data so processors can move at full speed. We enable DRAM scaling with industry-leading etch and deposition technologies, deep materials expertise, and tools optimized for speed and yield. By eliminating delays across development and manufacturing, customers bring next-generation memory to market faster. https://bit.ly/4kPApYR

High-NA EUV lithography represents a major leap in semiconductor manufacturing, enabling the ultra-fine features required by the next generation of advanced devices. Learn how our Aether® dry resist and development process, developed in partnership with industry leaders and customers, unlocks the full potential of high-NA EUV lithography. https://bit.ly/4gMXYh4

We are expanding our engineering and customer support presence in Boise, Idaho as DRAM enters a phase of greater architectural complexity driven by AI demand. Boise is home to Micron Technology , and proximity allows us to work directly inside customer fabs to address challenges in high-aspect-ratio etch, materials integration, and yield optimization at the point of need. This move strengthens our capabilities to stay close to our customers' roadmaps and is part of our multi-year strategy to expand and enhance our infrastructure to increase operational and innovation velocity. https://bit.ly/4rhl1qk

As computing workloads grow, memory technology must keep pace. In our latest Semi 101, we break down how DRAM functions as volatile “working memory” - why capacitors require periodic refresh, and how DDR generations (now DDR5) boost bandwidth and efficiency. We also peel back the layers of scaling trends, from tighter cell layouts to TSV-enabled HBM, to the transition to 3D DRAM for data-heavy applications like AI and HPC. https://bit.ly/4kwGNnG