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WikiChip
@WikiChip
The official WikiChip Twitter account. Hardware (logic), computer architectures, & semiconductor engineering. Technical.
New York, NYen.wikichip.orgJoined November 2016
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WikiChip
@WikiChip
Intel introduces Loihi 2, a 2nd gen neuromorphic research chip. First chip fabricated on their Intel 4 EUV process, Loihi 2 brings faster processing & synaptic operations, new algorithms, & higher resource density with a neurons count of 1 million. #Intel4
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Intel Introduces 2nd Gen Neuromorphic Research Chip: Loihi 2 on Intel 4 EUV Process
Intel introduces Loihi 2, its second-generation neuromorphic research chip. First chip fabricated on their Intel 4 EUV process, Loihi 2 brings faster processing and synaptic operations, new algorithm...
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WikiChip
@WikiChip
[S] Inside PFN's AI processor & the world's most power-efficient supercomputer. Packing 52B xTors across 3050 mm² of silicon, this accelerator was developed to give this Japanese startup a competitive advantage exclusively for its own internal hardware.
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Inside PFN's AI Processor And The World's Most Power-Efficient Supercomputer
[Subscriber Content] Inside Preferred Networks' AI processor and the world's most power-efficient supercomputer it powers.
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WikiChip
@WikiChip
A look at Esperanto's ET-SoC-1, the startup's first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores. #RISCV #7nm
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A Look At The ET-SoC-1, Esperanto's Massively Multi-Core RISC-V Approach To AI
A look at Esperanto's ET-SoC-1, the startup's first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom...
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WikiChip
@WikiChip
Marvell launches the OCTEON 10 DPU series. Fabricated on a 5 nm process, these chips integrate Neoverse N2 cores, AI acceleration, vector packet processing acceleration, a 1 terabit switch, and the latest DDR5 and PCIe 5.0 I/O interfaces. #5nm #Armv9
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Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Marvell launches the OCTEON 10 DPU series. Fabricated on a 5 nm process, these chips integrate Neoverse N2 cores, AI acceleration, vector packet processing acceleration, a 1 terabit switch, and the...
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WikiChip
@WikiChip
Arm introduces its Confidential Compute Architecture (CCA) which provides a mechanism for Realms, secure enclaves that may be used by any application in order to protect data in use from everything else on the system. #Armv9 #ConfidentialComputing
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Arm Introduces Its Confidential Compute Architecture
Arm introduces its Confidential Compute Architecture (CCA) which provides a mechanism for Realms, secure enclaves that may be used by any application in order to protect data in use from everything...
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WikiChip
@WikiChip
[S] With hybrid bonding inching towards production, here's a look at Trishul, Arm's first exploratory test chip - in collab with GF - that demos the feasibility of high-density 3D stacking using Arm's CoreLink CMN-600 extended to 3D. #12LP #HybridBonding
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A Look At Trishul: Arm's First High-Density 3D Logic Stacked Test-Chip
With hybrid bonding inching towards production, here's a look at Trishul, Arm's first exploratory test chip - in collaboration with GlobalFoundries - that demonstrates the feasibility of high-density...
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WikiChip
@WikiChip
AMD recently unveiled 3D V-Cache, their first 3D-stacked-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density. #HybridBonding #SoIC
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AMD 3D Stacks SRAM Bumplessly
AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding...
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WikiChip
@WikiChip
CMN-700 is Arm's latest high-perf cache-coherent mesh interconnect for servers, enabling SoC designs with twice the cores, half a GiB of cache, dozens of mem controllers, & support dozens of cache-coherent accelerators, chiplets, & processors. #Neoverse
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The Mesh Network For Next-Generation Neoverse Chips
Arm's CMN-700 is the company's latest high-performance cache-coherent mesh interconnect for the server market, enabling SoC designs with twice as many cores, as much as half a GiB of cache, dozens of...
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