WikiChip

@WikiChip

The official WikiChip Twitter account. Hardware (logic), computer architectures, & semiconductor engineering. Technical.

New York, NY
en.wikichip.org
Vrijeme pridruživanja: studeni 2016.
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tweetova

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  1. 28. lip

    Marvell launches the OCTEON 10 DPU series. Fabricated on a 5 nm process, these chips integrate Neoverse N2 cores, AI acceleration, vector packet processing acceleration, a 1 terabit switch, and the latest DDR5 and PCIe 5.0 I/O interfaces.

    10 proslijeđenih tweetova 35 korisnika označava da im se sviđa
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  2. 23. lip

    Arm introduces its Confidential Compute Architecture (CCA) which provides a mechanism for Realms, secure enclaves that may be used by any application in order to protect data in use from everything else on the system.

    11 proslijeđenih tweetova 42 korisnika označavaju da im se sviđa
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  3. 22. lip

    [S] Intel talks 10-nanometer DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.

    7 proslijeđenih tweetova 21 korisnik označava da mu se sviđa
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  4. 13. lip

    [S] With Intel's acquisition of eASIC in 2018, the company's latest product - codenamed Diamond Mesa - attempts to bridge the gap between full ASIC and FPGAs.

    1 reply 8 proslijeđenih tweetova 20 korisnika označava da im se sviđa
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  5. 11. lip

    [S] With hybrid bonding inching towards production, here's a look at Trishul, Arm's first exploratory test chip - in collab with GF - that demos the feasibility of high-density 3D stacking using Arm's CoreLink CMN-600 extended to 3D.

    4 proslijeđena tweeta 19 korisnika označava da im se sviđa
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  6. 7. lip

    AMD recently unveiled 3D V-Cache, their first 3D-stacked-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

    30 proslijeđenih tweetova 108 korisnika označava da im se sviđa
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  7. 25. svi

    Arm Tech Day Coverage: New ... -Little Core: Cortex-A510 -Big Core: Cortex-A710 -Flagship Big Core: Cortex-X2 -DSU-110 Cluster -Interconnects: CI-700 & NI-100 .

    27 proslijeđenih tweetova 69 korisnika označava da im se sviđa
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  8. 23. svi

    [S] The magnets under the icy lake.

    5 proslijeđenih tweetova 12 korisnika označava da im se sviđa
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  9. 22. svi

    CMN-700 is Arm's latest high-perf cache-coherent mesh interconnect for servers, enabling SoC designs with twice the cores, half a GiB of cache, dozens of mem controllers, & support dozens of cache-coherent accelerators, chiplets, & processors.

    7 proslijeđenih tweetova 24 korisnika označavaju da im se sviđa
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  10. 21. svi

    [S] Late last year Samsung ramped its 5LPE process. Here's a look at the details of the node and an update from Samsung Foundry on a few new roadmap nodes, 4nm improvements, and 3nm status.

    1 reply 8 proslijeđenih tweetova 26 korisnika označava da im se sviđa
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  11. 18. svi

    A look at the current state of leading-edge foundries for the first quarter of 2021.

    13 proslijeđenih tweetova 45 korisnika označava da im se sviđa
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  12. 16. svi

    [S] A look at Esperanto's ET-SoC-1, the startup's first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores.

    10 proslijeđenih tweetova 23 korisnika označavaju da im se sviđa
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  13. 13. svi

    The IEEE Symposium on High-Performance Chips announced the program for the conference. Presentations include AMD Zen 3 & RDNA2, Intel PV, Alder Lake & Sapphire Rapids, IBM next-gen Z, Arm N2, Nvidia DPU, Google VCU, Xilinx, and many many more.

    17 proslijeđenih tweetova 69 korisnika označava da im se sviđa
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  14. 13. svi

    In rolls out flagship premium performance 11th Generation Core Tiger Lake-based mobile processors with eight cores.

    4 proslijeđena tweeta 14 korisnika označava da im se sviđa
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  15. 13. svi

    WikiChip Fuse moves to a decaying paywall model.

    4 proslijeđena tweeta 14 korisnika označava da im se sviđa
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  16. 27. tra

    Arm launches its next-gen server CPUs: Neoverse N2 & Neoverse V1 (formerly Perseus and Zeus). Targeting high-performance servers and the HPC market, the new cores bring 1.4-1.5x higher IPC, SVE support, BFloat16, and the ARMv9 architecture.

    1 reply 15 proslijeđenih tweetova 67 korisnika označava da im se sviđa
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  17. 6. tra

    Intel launches 3rd Gen Xeon Scalable, formerly Ice Lake-SP. Fabricated on 10nm, these server chips offer eight memory channels, go up to 40 Sunny Coves and offer a 20% IPC improvement over the last gen.

    1 reply 14 proslijeđenih tweetova 38 korisnika označava da im se sviđa
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  18. 5. tra

    Arm Highlights Near-Term Roadmap

    1 reply 4 proslijeđena tweeta 27 korisnika označava da im se sviđa
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  19. 30. ožu

    A decade after the release of ARMv8, today Arm is launching the ARMv9 architecture for the next decade of compute, focusing on security and specialized acceleration.

    12 proslijeđenih tweetova 49 korisnika označava da im se sviđa
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  20. 22. ruj 2020.

    Arm updates its Neoverse roadmap with the Neoverse N2 & V1, introducing SVE support for the first time as well as bfloat16 operations. Like the Cortex-X, the Neoverse V-series will ease its power and area constraints in favor of higher perf.

    10 proslijeđenih tweetova 44 korisnika označavaju da im se sviđa
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