🐍 Diego R.

Cerebras Systems inside of Cline provides lightning fast inference inside your developer workflow. Here is a quick tutorial showing just how easy it is. There are lots of things worth waiting for. Inference results aren't among them. Build with the fastest...

176

Most #FPGA development for high-frequency trading systems is done in Verilog or VHDL. If you’re from an electronics background, that feels normal. But to a software engineer, it’s like writing an enterprise system entirely in assembly. Possible, yes. Pleasant? Not really. Why use FPGAs in HFT? They let trading firms process market data and execute trades with extremely low latency. FPGAs can be customized to handle high-speed data streams deterministically—something CPUs or GPUs struggle with. In ultra-competitive markets, that speed can literally be the difference between profit and loss. High-Level Synthesis (HLS) was supposed to make FPGA development more accessible. It helps—but only partially. While it introduces higher-level abstractions, it also adds new layers of complexity. Modern software engineering looks very different. Developers today benefit from vast ecosystems of open-source libraries, powerful package managers, build tools, and testing frameworks. These tools make complex systems manageable, allow rapid prototyping, and improve code reliability. FPGA development has historically lacked this richness — something that has provoked several lively debates at recent STAC Summits. This is where Clash comes in. Clash is a functional hardware construction language (HCL) that lets engineers describe circuits in a #Haskell-like language. Instead of manually wiring modules, you write high-level, type-safe functions that generate Verilog or VHDL automatically. Pure functions, strong typing, and property-based tests make circuits safer, easier to maintain, and faster to prototype—bringing some of the same productivity benefits software engineers enjoy today. As FPGA designs in HFT grow more complex, writing HDL gets even more painful. Functional alternatives like Clash could be the bridge that finally lets hardware design catch up with modern software practices—offering richer tooling, safer abstractions, and more maintainable ultra-low-latency systems. Chris Harris, an FPGA engineer who builds HFT systems, gave an excellent talk on Clash at the Tokyo STAC Summit, highlighting how these ideas are being applied in some of the trading systems he's currently working on. Are HCLs the next big thing in hardware engineering? Let's discuss at the next #STAC Summit. Register for free: https://lnkd.in/ekGAhJ4P

27

1 Comment

LMCache has joined the PyTorch Ecosystem, bringing powerful LLM inference acceleration through tight integration with vLLM. Developed at the University of Chicago, LMCache introduces open source Key-Value caching that reuses and shares KV caches across queries and engines, delivering up to 15× faster throughput for multi-round and document-based workloads. 🔗 Read the blog: https://hubs.la/Q03QQt5r0 #PyTorchFoundation #vLLM #OpenSourceAI #AIInfrastructure #LLM

382

5 Comments

I'm delighted to see two of Igalia's projects for RISE (RISC-V Software Ecosystem) highlighted in Ludovic Henry and Nathan Egge's presentation at the RISC-V Summit Europe. Find out more about our work on LLVM optimisation and testing in CI on the RISE blog (with more to come in the future of course!): https://lnkd.in/eemqeJge https://lnkd.in/etfYkbn8

89

🚨 Small number of poisoned samples can seriously compromise LLMs! I just read an eye-opening study by Anthropic, UK AISI, and The Alan Turing Institute titled “A Small Number of Samples Can Poison LLMs of Any Size.” Their core finding is astonishing: with as few as ~250 malicious documents, an attacker can successfully insert a “backdoor” into large language models (ranging from 600M to 13B parameters) — causing them to misbehave on specific trigger phrases — regardless of the total training data size or model scale. This marks a major shift from the earlier belief that an attacker must control a proportion of the dataset. Instead, this research shows that it’s the absolute number of poisoned samples that truly matters. The full technical paper — “Poisoning Attacks on LLMs Require a Near-constant Number of Poison Samples” — dives deeper into the experiments and implications. 📄 Read here: https://lnkd.in/gje8V-76 🎥 Watch a great explanation: https://lnkd.in/gMk68vj3 🙏 Thanks to Krish Naik for breaking it down so clearly!

34

2 Comments

Columnar File Readers in Depth: Structural Encoding Fantastic blog post about on-disk data structures when trying to store arrays, plus a lot of praise for parquet, which is holding up quite ok (albeit with some tuning) compared to lance. Also at some point you'll reach the stage where the format is optimized (seems there is still some work left for better compression) and you will also turn back to the operating system to saturate bandwidth.

16

1 Comment

In my latest #Zephyr video, I demonstrate how to connect OpenOCD to GDB and perform step-through debugging. It takes a little bit of configuring, but the toolchain is worth it for #embedded #programming. 👇👇👇 https://lnkd.in/e28zNd2z #IoT #microcontroller #ESP32 The Zephyr Project

212

4 Comments

The RISC-V vs ARM debate has become nothing more than tech tribalism that makes engineers feel virtuous while completely overlooking what actually determines project success in the real world. We've all encountered, 'RISC-V will democratize computing with its open-source model!' But let's be brutally honest: in 80% of commercial deployments, ecosystem availability beats architectural ideals every time. The countless hours spent battling incompatible RISC-V toolchains could have been invested in optimizing ARM-based solutions. And don't get me started on teams that select RISC-V for 'openness' only to find their custom ISA extensions have locked them into a single vendor more tightly than ARM's licensing ever could. I've observed directly projects hemorrhage 6 months just to get basic RISC-V compiler support working reliably for standard peripherals, while comparable ARM implementations reached production in 8 weeks leveraging battle-tested CMSIS drivers. The most ironic part? The 'open-source' narrative conveniently obscures that 70% of production RISC-V systems rely on proprietary extensions and commercial toolchains - you're essentially swapping ARM's licensing costs for RISC-V vendor support agreements. What we genuinely need is ruthless pragmatism: ARM when time-to-market and peripheral support are critical, RISC-V when custom accelerators or extreme cost constraints drive the design. This isn't compromise - it's engineering common sense. When your product launch is next quarter and you need functional WiFi, BLE, and security subsystems, every absent driver in the RISC-V ecosystem directly threatens your schedule. The next time you feel drawn to RISC-V for ideological reasons, ask yourself: Will this choice genuinely accelerate my development timeline, or am I volunteering to be a toolchain guinea pig? ⚖️ What single factor tipped the scales between RISC-V and ARM in your last project? Share your make-or-break decision criteria below - bonus points for how you'd evaluate the trade-off differently today! #RISCV #ARM #EmbeddedSystems #ProcessorArchitecture #EngineeringReality #EcosystemMaturity #TechChoices #DeveloperExperience #FPGA #SoC #CostOptimization #TimeToMarket

167

17 Comments

#google released FunctionGemma today, a lightweight, 270M-parameter variant built on the Gemma 3 architecture with a function-calling chat format. It is intended to be fine-tuned for task-specific function calling, and its compact size makes it practical for edge or resource-constrained deployments. Fine-tune it using open-source #NVIDIA NeMo: https://lnkd.in/gQhCyEtW

48

✨ Grateful to Bambordé Baldé and Quantum Formalism, Quantum Formalism CIC and everyone who joined the first session of our workshop on Physics-Informed Neural Networks (PINNs)! It was truly inspiring to share knowledge, exchange experiences, and see such engagement and curiosity from the community. 🚀 During the session, we covered PINNs in general, architectures, and how to build a PINN from scratch. We shared practical examples using PyTorch as well as with pinnfactory, the open-source framework I developed to simplify the creation of loss functions and the training of PINNs. 💻 Some of the topics we discussed included: - Automatic selection of rates in the PINN loss function - Best architectures and optimization strategies - Multi-Physics PINNs with transfer learning - Training using data points and collocation points This is just the beginning of a journey to deepen discussions and foster research and applications in this exciting field. 🙌 Thank you to everyone who participated and contributed with questions and insights. Looking forward to seeing you in the next session! 💡

50

2 Comments

On static Koopman operators: every ML approach, including transformers, at the final step represents output (y) as a sum of (possibly nonlinear) functions of input (x) i.e. lifting of x. In https://lnkd.in/gWXitqUB I introduced the notion of linear operators associated with maps between different spaces. The change of perspective is that now a lifting of output is related to lifting of input, providing a generalization of the standard approach. #KoopmanOperator #AI #ML #DynamicalSystems #ControlTheory

50

🚀 The first email of my newsletter is live! I’ve just published the kickoff article for a new series diving into the internals of the Go compiler: 👉 The Go Lexer: https://lnkd.in/dKcFadQE This post explores how Go’s lexer works — the first step in transforming source code into something the compiler can understand. In upcoming posts, I’ll be covering the parser, IR, SSA, and binary generation — taking a look under the hood of how Go code becomes an executable. If you enjoy understanding how things really work behind the scenes, you can read more (Go and not Go related) on my blog or subscribe to the newsletter here: 🔗 https://lnkd.in/dRZpv-As

76

8 Comments