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. 2020 Nov;587(7832):72-77.
doi: 10.1038/s41586-020-2861-0. Epub 2020 Nov 4.

Logic-in-memory based on an atomically thin semiconductor

Guilherme Migliato Marega  1   2 , Yanfei Zhao  1   2 , Ahmet Avsar  1   2 , Zhenyu Wang  1   2 , Mukesh Tripathi  1   2 , Aleksandra Radenovic  3 , Andras Kis  4   5
Affiliations

Logic-in-memory based on an atomically thin semiconductor

Guilherme Migliato Marega et al. Nature. 2020 Nov.

Abstract

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage1-3, thus promising to reduce the energy cost of data-centred computing substantially4. Although there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials5,6 such as semiconducting molybdenum disulphide, MoS2, could be promising candidates for such platforms thanks to their exceptional electrical and mechanical properties7-9. Here we report our exploration of large-area MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits in which logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and a functionally complete set of operations. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.

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Conflict of interest statement

Competing interests

The authors declare no competing financial interests.

Figures

Extended Data Figure 1
Extended Data Figure 1
Two-State retention time. Conductance G DS versus time. Blue curve – V PROG = -12.5V. Red curve - V PROG = +12.5V. Fitting of curve for predicting the trend of the decay using the following expression f(x) = A·xk. We expect that the device has a 10-year retention.
Extended Data Figure 2
Extended Data Figure 2
Additional characteristics of MoS2 FGFETs. a, Device variability. I DS versus V G curves for 6 different devices on the same die. b, Fresh I DS versus V G. Curves with small ±V G,MAX which is insufficient for inducing charge transfer into the floating gate memory. This shows the behavior of the FGFET in the initial state. c, I DS versus V G for different V DS. Red curve - V DS = 50mV. Blue curve - V DS = 100mV. Green curve - V DS = 250mV. Orange curve - V DS = 500mV. The progressive increase of the current without decreasing the memory window demonstrates that the memory effect is not due to capacitive charges in the contacts. d, I DS versus V G for different sweep rates. The decrease on the memory window in function of the sweep-rate. The decrease is most likely a result of a limit charge dynamics for charging and discharging the floating-gate.
Extended Data Figure 3
Extended Data Figure 3
Simplified band diagrams of MoS2 FGFETs. a, Energy band diagrams of different materials comprising the FGFET before being brought into contact. b, Programming of the floating gate memory with electron injection into the floating-gate (application of positive gate voltage and positive shift in the threshold voltage). c, Erase operation with electron extraction from the floating-gate (application of negative gate voltage and negative shift in the threshold voltage).
Extended Data Figure 4
Extended Data Figure 4
Floating gate endurance test. a, Each P/E Cycle is constituted of 100 ms positive 7.5 V pulse for the Erase operation and 100 ms negative -7.5V pulses for Programming. b, Each P/E Cycle is comprised of a 100 ms positive 10.0 V pulse for erasing and a 100 ms negative -10.0 V pulse for programming. Both measurements are taken using a constant V DS = 50 mV.
Extended Data Figure 5
Extended Data Figure 5
Example of the graphical estimation of the noise margin for the inverter programmed with V PROG = 8.5 V. V IL and V IH are defined as the points where the gain of the transfer curve is unitary. V OL and V OH are the point where the curve is reflected from the transfer curve towards the V OUT axis.
Extended Data Figure 6
Extended Data Figure 6
Circuit Schematic for a 2-Input NOR a; Circuit Schematic for a 2-Input NOR b; Logic over time for different programming states Q1, Q2. 33 – Constant LOW; 11 – Constant HIGH; 21 – Inverter A; 12 – Inverter B; 22 – NOR A,B.
Extended Data Figure 7
Extended Data Figure 7
3-Input NOR a; Circuit Schematic for a 3-Input NOR b; Logic over time for different programming states Q1, Q2, Q3. 111 – Constant HIGH; 211 – Inverter A; 112 – Inverter C; 122 – NOR B,C; 212 – NOR A,C; 221 – NOR A,B; 222 – NOR A,B,C
Extended Data Figure 8
Extended Data Figure 8
2-input logic-in-memory concept and interpretation a, 2-input schematic of the logic-in-memory concept; b, Interface model for input polarity control; c, NAND gate – Q1-4 = 22 11; d, NOR gate – Q1-4 = 23 32; e, XOR gate – Q1-4 = 33 33, by applying the De Morgan’s laws we derive the XOR canonical form.
Extended Data Figure 9
Extended Data Figure 9
Hardware and software implementation of the logic-in-memory programmer a; Hardware implementation of the 4-memory programmer. b; Hardware implementation of the 9-memory programmer. c; Software working diagram of the programming and test blocks d; Example of programming and test using a 9-memory programmed into the following state Q1-9 = 222 111 111 to perform a 3-Input NAND operation.
Extended Data Figure 10
Extended Data Figure 10
Raman characterization of monolayer MoS2. Raman spectra of transferred MoS2 from a single crystal from the same growth that the material used in the manuscript, using a 532 nm laser excitation and a 3000-line mm-1 grating. The observed difference between A1g and E2g Raman modes of MoS2 is consistent with a monolayer.
Extended Data Figure 11
Extended Data Figure 11
ADF-STEM image of monolayer MoS2. a, atomically-resolved STEM image shows the large field of view of the monolayer MoS2. Inset: Fast Fourier transform (FFT) amplitude spectrum further shows the crystalline monolayer MoS2 structure. b, the magnified filtered STEM image taken from a show the 2H crystal structure of monolayer MoS2. C, STEM simulation image of monolayer MoS2. The intensity line profiles along the dashed lines shows the peak positions of Mo-atoms and S-atoms in both panels b and c, respectively.
Extended Data Figure 12
Extended Data Figure 12
Floating-Gate transistor TEM cross-section a, wide-field view of the device b, magnified view of the contact area c, cross-section image of the gate stack consisting, from bottom to top: Pt bottom gate, HfO2 blocking oxide, Pt floating-gate, HfO2 tunnel oxide. MoS2 2D channel is on top of the gate stack.
Figure 1
Figure 1. In-memory device structure.
a, Three-dimensional view of a floating-gate memory device based on MOCVD-grown monolayer MoS2 with source (S) and drain contacts (D). The floating gate (FG) is separated from the MoS2 channel by a 7 nm thick HfO2 tunnel oxide layer and the bottom control gate (G) by a 30 nm thick HfO2 blocking oxide layer. b, Schematic of the device. c, Optical image of the fabricated floating-gate memory array, comprised of 8 memory cells (scale bar: 10 μm).
Figure 2
Figure 2. Characterization of non-volatile memories.
a, Transfer characteristic of the floating-gate transistor (I DS vs. V G) acquired for two different gate voltage sweep directions. The variation of the threshold voltage V TH, the memory window, is estimated to be 10.6 V. b, Output characteristics (I DS vs. V DS) of the floating-gate transistor in the ON state, after having been programmed using different values of the programming voltage V PROG. c, Time-dependence of the device conductance for different levels of programming voltage V PROG. Retention measurements showing multilevel states of the normalized conductance G DS versus time as a function of the programming voltage (V PROG ranging from -12.5 V to 12.5 V). d, Demonstration of fine control over the conductance state of the memory using voltage pulses applied to the gate. Main plot shows the evolution of the memory device conductance G DS as a function of the number of pulses. Potentiative pulses applied to the gate (-5 V amplitude, 10 ms duration and 1s rest time) can be used to increase and fine-tune the conductance. Depressive pulses (+5 V amplitude, 10 ms duration and 1s rest time) can reset the device. The conductance measurement is performed at the end of the rest time period. Before the first pulse, the memory was initialized with a reset voltage VPROG = 12.5 V for programming the initial memory state into the floating gate.
Figure 3
Figure 3. Programmable inverter based on a MoS2 memory cell.
a, Schematic of the programmable inverter, different states of the device and the inverter truth table. b-d, Illustration of the discrete memory states used for programmable behavior and the corresponding circuit diagrams: b, Insulating state of the MoS2 channel (Q = 1, memory state 0). c, semiconducting state with a continuously tunable conductance of the MoS2 channel (Q = 2, memory states 0 or 1). d, Conductive state of the channel (Q = 3, memory state 1). e, Programmable output (V OUT) curves of the inverter and the inverter voltage gain as a function of the input voltage (V IN), for different programming conditions. f, Evolution of the inverter noise margin (NML and NMH) as a function of the programming voltage. g, Time traces showing stability of the output voltage for the three different configurations of the programmable inverter. Red: input voltage (V IN), orange: constant 0 state, blue: inverter operation, green: constant 1 state.
Figure 4
Figure 4. Logic-in-memory.
a, Photograph of a fabricated 12 × 12 mm die with logic-in-memory cell arrays and schematics of the 2-input and 3-input logic-in-memory cells b, System level operation of two 2-input cells to form a half-adder. XOR programmed as Q 1-4= 2 with inputs to memories Q 3 Q 4 inverted. NAND programmed as Q 1-2= 2, Q 3-4= 3 output is inverted to form AND logic. c, Time traces showing stability of the output voltage for the NAND operation of the 3-input unit cell. For this configuration, memories are programmed as following Q 1-3 = 2, Q 4-9 = 3. The transfer curves of each state can be seen in SI 15.
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