Jakub Rewieński

Most RTL engineers view Credit-Based Flow Control as a architectural solution for avoiding data drops and managing FIFO depths. As Physical Design engineers, we see it as something completely different: A physical footprint equalizer. When you're routing across large sub-modules or a multi-die interposer, pure backpressure (Valid/Ready handshakes) creates a silent nightmare during Physical Design. 𝙃𝙚𝙧𝙚 𝙞𝙨 𝙬𝙝𝙮 𝘾𝙧𝙚𝙙𝙞𝙩-𝘽𝙖𝙨𝙚𝙙 𝙁𝙡𝙤𝙬 𝘾𝙤𝙣𝙩𝙧𝙤𝙡 𝙢𝙖𝙩𝙩𝙚𝙧𝙨 𝙟𝙪𝙨𝙩 𝙖𝙨 𝙢𝙪𝙘𝙝 𝙩𝙤 𝙋𝙣𝙍 𝙖𝙣𝙙 𝘾𝙏𝙎 𝙖𝙨 𝙞𝙩 𝙙𝙤𝙚𝙨 𝙩𝙤 𝘼𝙧𝙘𝙝𝙞𝙩𝙚𝙘𝙩𝙪𝙧𝙚: 𝗧𝗵𝗲 𝗖𝗼𝗺𝗯𝗶𝗻𝗮𝘁𝗶𝗼𝗻𝗮𝗹 𝗕𝗮𝗰𝗸𝗽𝗿𝗲𝘀𝘀𝘂𝗿𝗲 𝗧𝗿𝗮𝗽: Standard 𝗿𝗲𝗮𝗱𝘆 signaling often creates a backward combinational path from the receiver to the sender. Across long distances (e.g., 2–4mm of metal), this single signal introduces long wire RC delay, forcing synthesis to buffer aggressively. The result? Unnecessary clock tree capacitance, congestion around ports, and severe setup time violations. 𝗙𝗹𝗼𝗽-𝘁𝗼-𝗙𝗹𝗼𝗽 𝗣𝗶𝗽𝗲𝗹𝗶𝗻𝗶𝗻𝗴: Credit-based systems decouple the forward data path from the backward status loop. Credits allow you to fully register both the 𝙫𝙖𝙡𝙞𝙙 path and the 𝙘𝙧𝙚𝙙𝙞𝙩_𝙧𝙚𝙩𝙪𝙧𝙣 path. For PD, flop-to-flop paths mean clean retiming, predictable wire budgeting, and zero long combinational feedback paths. 𝗙𝗹𝗼𝗼𝗿𝗽𝗹𝗮𝗻𝗻𝗶𝗻𝗴 & 𝗗𝗶𝘀𝘁𝗮𝗻𝗰𝗲 𝗔𝗴𝗻𝗼𝘀𝘁𝗶𝗰 𝗥𝗼𝘂𝘁𝗶𝗻𝗴: Adding latency (pipeline stages) to a valid/ready path breaks the protocol. Adding pipeline stages to a credit loop only requires bumping the initial credit count by 2x wire latency stages. This allows PD teams to push blocks farther apart during floorplanning without rewriting control logic or suffering throughput drops. 𝗣𝗼𝘄𝗲𝗿 & 𝗔𝗿𝗲𝗮 𝗥𝗲𝗹𝗶𝗲𝗳: Eliminating long combinational backpressure loops prevents the PnR tool from inserting massive buffer trees across high-density routing channels—saving dynamic clock power and silicon area. 𝗡𝗲𝘅𝘁 𝘁𝗶𝗺𝗲 𝘆𝗼𝘂𝗿 𝗺𝗶𝗰𝗿𝗼-𝗮𝗿𝗰𝗵𝗶𝘁𝗲𝗰𝘁 𝗮𝘀𝗸𝘀 𝘄𝗵𝘆 𝘆𝗼𝘂 𝗽𝗿𝗲𝗳𝗲𝗿 𝗖𝗿𝗲𝗱𝗶𝘁-𝗕𝗮𝘀𝗲𝗱 𝗙𝗹𝗼𝘄 𝗖𝗼𝗻𝘁𝗿𝗼𝗹 𝗼𝘃𝗲𝗿 𝗩𝗮𝗹𝗶𝗱/𝗥𝗲𝗮𝗱𝘆 𝗵𝗮𝗻𝗱𝘀𝗵𝗮𝗸𝗲𝘀, 𝘁𝗲𝗹𝗹 𝘁𝗵𝗲𝗺: 𝗜𝘁’𝘀 𝘁𝗵𝗲 𝗱𝗶𝗳𝗳𝗲𝗿𝗲𝗻𝗰𝗲 𝗯𝗲𝘁𝘄𝗲𝗲𝗻 𝗰𝗹𝗼𝘀𝗶𝗻𝗴 𝘁𝗶𝗺𝗶𝗻𝗴 𝗮𝘁 𝟯 𝗚𝗛𝘇 𝘃𝘀. 𝘀𝗽𝗲𝗻𝗱𝗶𝗻𝗴 𝘁𝗵𝗿𝗲𝗲 𝘄𝗲𝗲𝗸𝘀 𝗳𝗶𝗴𝗵𝘁𝗶𝗻𝗴 𝗿𝗼𝘂𝘁����𝗻𝗴 𝗰𝗼𝗻𝗴𝗲𝘀𝘁𝗶𝗼𝗻 & 𝗘𝗖𝗢𝘀. #PhysicalDesign #SemiconductorDesign #VLSI #RTLDesign #ASIC #ChipDesign #TimingClosure

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https://lnkd.in/djGdYXyC - most performant compression programs for the first gigabyte of Wikipedia use Transformer architecture, four of top entries. What's interesting there is that current most performant program, fx2-cmix-transformer, uses small transformer model with only 6M parameters, pretrained separately. And it beats online-trained transformer model (nncp, currently fourth) in all regards: it has less parameters, it runs faster, it needs less energy (nncp needs GPU) and, most importantly, it squeezes text to 0.768 bits per byte, compared to 0.85 bits per byte of nncp. This is history rhymes itself. LHA was released in 1991 and it used dynamic Huffman compression, where statistics got updated during compression and code table had to be rebuilt from time to time. Dynamic Huffman compression does not need to store the code table and it works online. Then, after about two years, PKZIP was released. It used static Huffman compression, but stored code table in compressed format, using only code lengths and Shannon-Fano algorithm to recover encodings. It compressed better and worked much faster. Most LZSS+Huffman compressors use static Huffman since then. I think that new large text compression benchmark contenders will use precomputed models as well.

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Multi-radio wireless prototypes often stall at RF integration due to antenna coupling, isolation issues and band retuning requirements. These challenges - along with certification surprises - slow everything down. 👉 Download: https://lnkd.in/dhb5iqFw Our new design guide shows how to reproduce a compact 50×50 mm Nordic Thingy:91 X reference design with dedicated antennas per radio (cellular, GNSS, Wi-Fi 6, BLE) and a MIPI-controlled switch for fast, software-tunable LTE bands. It includes layout details, matching networks, and OTA TRP/TIS data to de-risk certification. Accelerate your next asset tracker, industrial sensor, or wearable without RF guesswork. #RFDesign #NordicThingy91X #VirtualAntenna #CellularIoT #GNSS #WiFi6 #BluetoothLE #ProductDevelopment

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A7676E is the LTE450 & Cat 1 module that supports wireless communication modes of LTE-FDD/GSM/ GPRS/EDGE. It also supports LTE 450MHz frequency band and supports maximum 10Mbps downlink rate and 5Mbps uplink rate.  A7676E adopts LCC+LGA form factor and is compatible with SIM7000/SIM7070 series (NB/Cat M modules), and SIM800F (2G modules), which enables smooth migration from 2G/NB/CAT-M products to LTE Cat 1 & 450Mhz products, and greatly facilitates more compatible product design for the customer needs.  A7676E is optimized for LTE Cat 1bis and supports multiple built-in network protocols and the drivers for main operation systems (USB driver for Windows, Linux and Android). A7676E also supports Dual SIM, VoLTE and GNSS* to adopt various usage scenario. Due to the latest generation LTE Cat1 chipset, A7676E offers ultra-low power consumption and integrates abundant industrial standard interfaces with powerful expansibility, such as UART, USB, I2C and GPIO, which makes it perfectly suitable for main IOT applications such as telematics, POS, surveillance devices, industrial routers, and remote diagnostics etc. Product Advantages - Compact size with abundant interfaces & ultra-low power consumption - Supports Dual SIM, VoLTE and GNSS function(optional) - Abundant software functions: FOTA, LBS, SSL - Form factor is compatible with the SIM7070E (LTE450 Cat M1 & NB2 module) #a7676 #a7676e #Cat1 #4g #lte4g #iot #wireless #4gmodule #cat1module #pos #gnss #LTE #router

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MT7621A has 96 GPIOs. We still ran out of GPIOs. Several of these GPIOs are multi-function. The design has several subsystems. No display. So it needs several LEDs. Also has several modules that need switching and reset; controlled via GPIO. So we used a GPIO expander. Never thought we would. Modern MCUs and MPUs have so many IOs. Yet we did use a MCP23017 after evaluating a few of these Setup addressing Put it on a I2C bus Linux makes it so easy, just add the drivers All GPIOs are ready to go! #GPIO #PortExpander #MT7621A #MCP23017 #linux #openwrt

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After our last post, someone asked the obvious question: can RTLPreCheck actually find bugs, or does it just prove things that were already correct? Fair question. So we ran the full BOOM SoC, all 552 SystemVerilog files, and injected a microarchitectural bug into the reorder buffer. Not a timing violation. Not a lint warning. A deep architectural defect that lives at the intersection of two independent recovery paths and never surfaces in simulation. Of the 552 files, 268 modules received automated formal analysis. The remainder are stateless: monitors, SRAM macros, combinational leaf cells, thin wrappers, and dedup variants. Stateful formal properties don't apply to them. The 268 modules are where the design's behavior lives. Traditional formal verification asks: given this spec, does the design comply? We asked the opposite question: given this design, what must be true? A cardiologist doesn't ask your heart to describe itself. The signal patterns on the EKG reveal the structure (chambers, valves, rhythm, pathology) without a single word from the patient. RTLPreCheck reads RTL the same way. The structure reveals what every module does and what properties it must satisfy. No spec. No annotations. No naming conventions. The structural analysis covers the majority of patterns autonomously. Where gaps remain, a tightly constrained AI fills them, working from proven structural primitives that the deterministic pipeline has already established. It learns, but never decides. The formal solver confirms or rejects every proposal. Nothing reaches the output without passing K-induction. 46 minutes. 1,732 properties proven across 268 modules. 9,084 cross-module boundary edges discharged automatically, every upstream guarantee matched to every downstream assumption with zero manual assume-guarantee wiring. And the injected bug? Caught in 17 seconds with a concrete counterexample trace. RTL in. Proven properties out. Bugs caught. Every proof ran on an open source formal solver. The generated properties are standard SVA, portable to any commercial formal tool. Later this week we move beyond out-of-order cores. Same tool, different architecture class. Stay tuned.

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Most FPGA embedded engineers encounter a similar challenge: getting reliable host communication in place without spending days doing low-level work. Our FPGA engineer appreciates having ready-made designs for both XDMA and QDMA, together with the WinDriver samples. The combination makes life easier and saves effort in both the low-level programming and the FPGA design work. Moreover, it allows testing user-mode and kernel-mode paths on Windows or Linux without diving into kernel programming. Learn more here 👉 https://lnkd.in/dYs6dZ5F

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WIN SOURCE | High-Speed Differential Driver Selection Guide Choosing the right differential driver shapes the signal integrity, bandwidth budget, and system robustness of any high-speed analog front end. Our latest guide compares AD8131, AD8132, and AD8138—three Analog Devices drivers widely used in data acquisition, instrumentation, and communication systems. 🔍 Single-ended-to-differential, differential gain & precision signal-conditioning use cases 📐 Bandwidth, distortion, noise, supply-rail & drive-strength comparison 🧩 Layout, gain-setting, termination & common-mode control tips 👉 Read the full analysis: https://lnkd.in/g8h47fkX #WINSOURCE #DifferentialDriver #AnalogDesign #ComponentSelection #SignalIntegrity #HighSpeedDesign #AnalogDevices

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A funny thing happens in engineering. Engineers spend months discussing: FPGA resources RF performance Processing capability Bandwidth Power consumption Then the customer joins the meeting. And asks: "When can I get a working system?" Not: How many LUTs? How many DSPs? Which FPGA family? What process node? Just: "When can I use it?" That doesn't mean the technology isn't important. It absolutely is. But it reminds us that customers and engineers often view the same product from different perspectives. Engineers optimize architecture. Customers optimize outcomes. In SDR and wireless communications, this creates an interesting challenge. The technically best solution is not always the one that gets adopted. Sometimes the winning solution is the one that: Integrates faster Requires less development effort Is easier to deploy Is easier to maintain This way of thinking influenced the development of FJM30. The goal was not simply to create another RF device. The goal was to reduce the amount of system-level work required to build a practical SDR platform. Because at the end of the day, most customers don't buy chips. They buy solutions. 👉 What is the biggest difference you've noticed between what engineers care about and what customers care about? #SDR #RFDesign #FPGA #WirelessCommunications #EmbeddedSystems #Engineering #ProductDevelopment #FJM30

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