Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on: Bu...

Classroom - Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center and embedded applications.The emphasis of this course is on:Usi...

Classroom - Compact DSP Design for Versal Using Vitis Model Composer (PLC2 version)
With MATLAB™ and Simulink™, Vitis™ Model Composer offers several toolboxes for DSP development.The HDL toolbox is based on VHDL/Verilog code generation and the HLS toolbox the C/C++-based code generation using Vitis™ ...

Classroom - Compact DSP Design for Versal Using Vitis Model Composer (PLC2 version)
This course provides experience with using the Vitis™ Model Composer tool for model-based designs focusing on UltraScale+™ and Versal™ technologies. With MATLAB™ and Simulink™,Vitis™ Model Composer offers the DSP deve...

Classroom - Compact Vitis AI (PLC2 version)
This course presents the Vitis AI development Toolkit for the AI inference on Xilinx Hardware platforms in conjunction with DNN algorithms, model training, associated frameworks for development and deploying it on Alv...

Classroom - Compact Vitis for Acceleration (PLC2 version)
Sequential processing or data path speed is a bottleneck in many high-end systems based on CPUs whereas FPGAs provide massive parallel data processing along with optimized data path. A system with CPU and FPGA combina...

Classroom - Compact Vitis for Software Designers (PLC2 version)
This course focuses on the embedded software related topics of the Xilinx Vitis Unified Software Platform. Vitis operation and project setup for various use cases with the Zynq 7000 SoC and Zynq Ultrascale+ MPSoC are ...

Classroom - Compact Vitis HLS (PLC2 version)
Since the invention of FPGAs, the development methodology was continuously evolving from schematic entry towards RTL based system modeling A downside of these methods is the requirement, that not only the desired func...

Classroom - High-Level Synthesis with the Vitis HLS Tool
This course provides a thorough introduction to the Vitis™ High-LevelSynthesis(HLS) tool.The focus is on:Covering synthesis strategies and features Applying different optimization techniques Improving throughput, area...

Classroom - Professional DSP Design Using Vitis Model Composer (PLC2 version)
This five-days workshop includes teaching DSP and acceleration development methods for both generic FPGAs and Versal™ adaptive SoC technologies using the AMD Vitis™ Tools Model Composer, which needs to be used with MA...