Pune, Maharashtra, India
1K followers 500+ connections

Join to view profile
Shri Ramdeobaba College of Engg. and Management

About

Software Engineer with 8+ Years of Experience in Embedded Linux and C Application…

Contributions

Join now to see all contributions

Activity

Join now to see all activity

Experience & Education

  • Johnson Controls

View Arjun’s full experience

See their title, tenure and more.

or

By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy.

Licenses & Certifications

Volunteer Experience

  • Vice-Secretary

    Parindey Youth Foundation

    - 1 year 1 month

    Social Services

    Its a youth foundation which works in betterment of society and we are wanting to work in sector of sex equality and women empowerment.
    Our basic motto is to stand up for HUMANITY.

Publications

  • A Holistic Comparison of Static VC Allocation Versus Dynamic VC Allocation Based NoC Routers

    IEEE

    Router architectures advocating the use of static as well as dynamic virtual channel allocation have been proposed in the literature. However, the comparisons between the two have primarily focused on simulation set-up, largely using synthetic benchmarks. In this work, we present an apple-to-apple comparison of the dynamic and static VC allocation based routers for network performance. We compare the static VC allocation and dynamic VC allocation based routers for real and synthetic benchmarks…

    Router architectures advocating the use of static as well as dynamic virtual channel allocation have been proposed in the literature. However, the comparisons between the two have primarily focused on simulation set-up, largely using synthetic benchmarks. In this work, we present an apple-to-apple comparison of the dynamic and static VC allocation based routers for network performance. We compare the static VC allocation and dynamic VC allocation based routers for real and synthetic benchmarks as well as their implementations. The performance of the two routers has been compared for different routing algorithms, topologies, packet sizes and input port configurations. We observe that for all synthetic traffic patterns, except uniform traffic, static VC allocation based router outperforms the dynamic VC allocation based router. We also observe that in almost all PARSEC benchmark applications, except Blackscholes and Bodytrack with DOR routing, the simplified EVA router outperforms the dynamic VC allocating router. In our ASIC implementation, we observe a clock frequency improvement of 20.2% and power reduction of 19.6% for the static VC allocation based router over the dynamic VC allocation based router.

    Other authors
    See publication

Projects

  • Comparative study safety critical system using MPU and Non-MPU model

    -

    -Study of Cortex-M3 MPU setup.
    -Study of MPU port template of FreeRTOS.
    -Tweaking the template as per application.
    -Tweaking Linker script.
    -Tested Standard Gas Station Case study available in software primer book of David Simmons.
    -Study Toyota's Unintended Acceleration Case and tried to corrupt global data and cause stack overflow using MPU to see whether our system is robust or not to handle these issues.
    -Platform such as FreeRTOS+IO, LPCOpen were explored and used.

  • Design and implementation of Network-on-chip architecture with mesh Topology

    -

    This project aims at redesigning the communication fabric between the cores in multiprocessor SOC i.e. system on chip. For establishing the network between the cores Network Interconnects (NI) and Routers have being designed.
    Network on Chip architecture is much similar to packet-switched communication.
    The NI comprises of packing unit and de-packing unit, where packing unit takes up the responsibility to generate packets for network request and de-packing unit takes up the responsibility…

    This project aims at redesigning the communication fabric between the cores in multiprocessor SOC i.e. system on chip. For establishing the network between the cores Network Interconnects (NI) and Routers have being designed.
    Network on Chip architecture is much similar to packet-switched communication.
    The NI comprises of packing unit and de-packing unit, where packing unit takes up the responsibility to generate packets for network request and de-packing unit takes up the responsibility to unpack the packet which is intended for the core after travelling the network to core feasible format.
    The Router on other hand is a five port device (North, South, East, West, Self) with crossbar and arbiter, Route Compute and Virtual Channel allocator to decide the path for packet to transverse through the network to destined core.
    For testing of experiment I have designed a core made up pseudo-Random number generator.
    The core is assumed to be standard of 32-bit and packet format for network is of 68-bit.

Languages

  • English

    -

  • Hindi

    -

  • Marathi

    -

Organizations

  • St.Vincent Pallotti College of Engineering & Technology

    Assistant Professor

    -

  • Indian Institute of Technology, Gandhinagar

    Project Intern

    -

Recommendations received

12 people have recommended Arjun

Join now to view

More activity by Arjun

View Arjun’s full profile

  • See who you know in common
  • Get introduced
  • Contact Arjun directly
Join to view full profile

Other similar profiles

Explore collaborative articles

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

Explore More

Others named Arjun Gour in India

44 others named Arjun Gour in India are on LinkedIn

See others named Arjun Gour

Add new skills with these courses

See all courses