Join Chris Petersen's team as a Senior Principal Technologist - Memory! This role sits at the intersection of architecture, customer engagement, and product definition, shaping Astera Labs’ next-generation data center memory solutions. You will: ✅ Drive architecture and definition of future memory products leveraging expertise in CXL, PCIe, DRAM, and SOC memory sub-systems. ✅ Engage directly with customers to influence product features, roadmap, and solve bottlenecks in hyperscale data centers. ✅ Collaborate cross-functionally across silicon, software, and systems teams to deliver full-stack solutions. ✅ Pitch cutting edge technology solutions to customers and industry partners. We're looking for a creative, customer-facing technologist with 10+ years in memory-related solutions, someone who wants to shape the future of rack-scale AI connectivity at a company that’s building what's next. Apply today: https://lnkd.in/gHHyjtcC #Hiring #AsteraLabs #Memory #CXL #PCIe #Semiconductors #AI #DataCenter #SiliconValleyJobs
Astera Labs
Semiconductor Manufacturing
Santa Clara עוקבים, CA 48,777
Purpose-Built Connectivity for Rack-Scale AI
עלינו
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
- אתר אינטרנט
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http://www.asteralabs.com
קישור חיצוני עבור Astera Labs
- תעשייה
- Semiconductor Manufacturing
- גודל החברה
- 501-1,000 עובדים
- משרדים ראשיים
- Santa Clara, CA
- סוג
- חברה ציבורית
- הקמה
- 2017
- התמחויות
מיקומים
עובדים ב- Astera Labs
עדכונים
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“…Astera hasn't just built a bigger PCIe switch. Scorpio is equipped with many of the same in-network compute capabilities as Nvidia's NVSwitch, which help to accelerate collective communications.” — Tobias Mann, The Register Astera Labs’ new Scorpio 320 Lane Fabric Switch is redefining what PCIe can do for AI infrastructure. 🚀 In his latest article, Tobias highlights how Astera Labs is extending PCIe beyond traditional connectivity with in-network compute capabilities that help GPUs spend more time generating tokens — and less time waiting on the network. By moving collective communications into the switch itself, Scorpio enables more efficient scale-up architectures while supporting vendor-agnostic AI deployments. Read the full article here: https://lnkd.in/gjS7xf8S #AI #DataCenter #Semiconductors#AsteraLabs #ScorpioFabricSwitch #Hypercast #TheRegister
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We are thrilled to share that our co-founders Jitendra Mohan, Sanjay Gajendra, and Casey Morrison have won EY World Entrepreneur Of The Year 2026! 🌍🏆 After being named National U.S. EY Entrepreneurs of the Year, they went on to compete against visionary leaders from 47 countries and territories at the global competition in Monaco — and took home the world title. This recognition reflects what Astera Labs is all about – bold vision, relentless execution, and a commitment to raising the bar together – as we continue to drive purpose-built rack-scale AI connectivity. Our sincere thanks to EY for this incredible honor, and a big congratulations to all Class of 2026 finalists who are shaping the future! And – we’re just getting started. Read the press release: https://lnkd.in/g8VZFvey #EY #EntrepreneurOfTheYear #AsteraLabs #Leadership #Innovation #AIInfrastructure
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You’re invited to join Thad Omura and Kishore Atreya for an exclusive fireside chat at Computex 2026: “Accelerating the NVIDIA NVLink Fusion Ecosystem: How Astera Labs and NVIDIA Are Bringing the Vision to Life” In this can’t-miss session, you will: ✅ Explore how scale-up infrastructure must evolve to meet the demands of next-generation AI models ✅ Understand how NVLink Fusion is redefining accelerator connectivity ✅ Discover how Astera Labs is enabling the ecosystem with purpose-built, high-performance solutions 📅 June 3 | 11:00 AM - 11:30 AM 📍 Astera Labs' Booth: TaiNEX 1, Room 303 (3rd Floor) Secure your spot and be part of the conversation shaping the future of AI infrastructure. https://lnkd.in/d9tbcXi2 #Computex2026 #NVLink #NVLinkFusion #AIInfrastructure #DataCenter #AsteraLabs #NVIDIA
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We're excited to see Jitendra M., Sanjay Gajendra, and Casey Morrison represent #BayAreaEOY and the U.S. at the EY World Entrepreneur Of the Year awards this week! It is an honor to be amongst such an inspiring group of innovators who are shaping the future of entrepreneurship on a global stage. Thanks to EY for helping tell their story. Check out the clip below and catch the full videos here: https://lnkd.in/gSHbcfw #EOY #WEOY #Entrepreneurship #Leadership #EY
“What is one bold prediction on how Astera Labs will be part of shaping the future?” I posed this to Casey Morrison and his answer was all about access. Scaling connectivity so it reaches smaller businesses, enterprises and smaller satellite data centers, not just the largest players. Because the future of tech isn’t just built at scale…it’s distributed. Curious what you think? Watch our full conversation here: https://lnkd.in/gNHT5VEW
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Heading to COMPUTEX TAIPEI 2026? Stop by the Astera Labs booth for expert-led sessions on the technologies powering rack-scale AI infrastructure. Here’s this year’s speaker lineup: 🔹 The New Engine Driving Frontier AI Forward — Caleb Shetland 🔹 The Evolving Boundary Between Copper and Optical — Jignesh Shah 🔹 Streamline, Automate & Accelerate Hardware Workflows with COSMOS Tools — Michael Ocampo 🔹 Inference Tokenomics: Making Every Token Count with KV Cache Optimization — Ahmad Danesh 🔹 Next-Gen Retimers for AI Systems — Connie Lu 🔹 Scaling 200G/Lane Ethernet : Advantages of Standard-Footprint Designs — Casey McCrea 📍 Hall 1, Room 303, Third Floor 📅 June 2–5 ⏰ Sessions running daily from 11 a.m.– 4:00 p.m. View the full schedule and plan your visit: https://lnkd.in/d9tbcXi2 #Computex2026 #AsteraLabs #AIYourWay #AIInfrastructure #RackScale #DataCenter #Connectivity #CXL #Innovation
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Join us at COMPUTEX TAIPEI 2026 for the Astera Labs Happy Hour! 🍸 Grab a drink, enjoy some music, and experience AI Your Way, with live demos of our purpose-built rack-scale connectivity solutions. Stop by our booth to meet with our connectivity experts, check out live demos, and see how Astera Labs is enabling the next generation of AI infrastructure at rack scale. Looking forward to seeing you there! 📅 June 3 | 3:00 – 5:00 PM 📍 TaiNEX 1, Hall 1, Room 303 (Third Floor) #Computex2026 #AsteraLabs #AIYourWay #AI #AIInfrastructure #DataCenter #RackScale #Connectivity #Innovation
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AI Your Way. Purpose-built Rack-scale Connectivity. In her blog, Paroma Sen shares how this statement goes beyond positioning—it reflects our company philosophy. Astera Labs is committed to enabling every path to AI, supporting diverse architectures, protocols, and deployment models across the ecosystem. From silicon to systems to software, our integrated platform delivers purpose-built connectivity across the rack—powering AI that is performant, efficient, secure, and reliable. As AI scales, flexibility and choice matter more than ever. And we’re here to make it possible—your way. 🔗 Read the blog: https://lnkd.in/gVDSDQhd #AILabs #AIInfrastructure #Connectivity #Datacenter #Innovation #Computex2026
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We’re hiring: Physical Design Manager – Toronto At Astera Labs, physical design enables the silicon behind the world's largest AI clusters. It's not back-end implementation — it's a core differentiator. We're looking for someone who has led teams through multiple tapeouts at advanced nodes and can drive complex ASIC implementation from floorplan through GDSII. You'll own execution for our Signal Connectivity Group, such as retimers and signal conditioning solutions deployed across hyperscale data centers. We're looking for an experienced Physical Design (PD) leader who can: ✅ Drive full-chip physical design execution from floorplan through tapeout at advanced nodes ✅ Build and scale a high-performing PD team in Toronto ✅ Integrate high-speed SerDes, analog IP, and hard macros into complex SoC designs ✅ Partner across RTL, DFT, STA, and verification to drive design convergence ✨ If you want a high-impact opportunity to build a world-class physical design team and shape the future of rack-scale AI connectivity, apply today: https://lnkd.in/g9Yw-Ey7 #PhysicalDesign #Hiring #AsteraLabs #AI #Semiconductors #EngineeringJobs #Toronto
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“The Scorpio X-Series launch signals a meaningful evolution in how AI infrastructure vendors are defining the role of the fabric switch. Rather than competing on raw bandwidth or port density alone, Astera Labs is embedding compute intelligence directly into the switching silicon in response to the specific demands of mixture-of-experts (MoE) architectures that now dominate frontier model development.” - Brendan Burke, The Futurum Group In his article, Brendan explores how Astera Labs is positioning its fabric switches to improve GPU utilization and token economics for production AI deployments. Read the full article: https://lnkd.in/gFeMJUUA #AI #DataCenter #Semiconductors #ArtificialIntelligence #ScorpioFabricSwitch #Hypercast #AsteraLabs #Futurum
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