VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
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Updated
Apr 4, 2025 - VHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Image Processing Toolbox in Verilog using Basys3 FPGA
Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
VHDL Guide
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Trying to verify Verilog/VHDL designs with formal methods and tools
cryptography ip-cores in vhdl / verilog
Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core
The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
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