Verilator open-source SystemVerilog simulator and lint system

XLS: Accelerated HW Synthesis

A repository of gate-level simulators and tools for the original Game Boy.

Verilog to Routing -- Open Source CAD Flow for FPGA Research

SystemVerilog compiler and language services

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS (archived)

A Just-In-Time Compiler for Verilog from VMware Research

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

A modern and open-source cross-platform software for chips reverse engineering.

A configurable C++ generator of pipelined Verilog FFT cores

A utility for Composing FPGA designs from Peripherals

Open source software for chip reverse engineering.

A C++ to Verilog translation tool with some basic guarantees that your code will work.

TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits

A series of CORDIC related projects

Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

FTDI FT600 SuperSpeed USB3.0 to AXI bus master

SDRAM controller with AXI4 interface