A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Vending Machine implementation on FPGA.
Designing and Modelling of an Intelligent Traffic Signal Controller using FSM in Verilog HDL
Spring 2024 NYCU Integrated Circuit Design Laboratory (ICLAB)
2D Platformer on Basys3 FPGA
TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board
Complex Adder with Seven Segment Display
An automatic traffic light controller is designed and simulated using the concept of Finite State Machine in ModelSim.
This repository consists of verilog codes for Digital VLSI Lab (EC39004), IIT KGP.
Door Lock with provision to set the password in Real Time
This repository contains all the necessary Verilog code and supporting files to synthesize the 8-bit soft-core processor on an FPGA. The code is well-commented, following best practices in digital design to ensure clarity and maintainability.
Implementation of Verilog and Finite state Machine
Basic tools, methods and procedures to design combinational and sequential digital circuits and systems. Topics include number systems, Boolean algebra, logic minimization, circuit design, memory elements, and finite state machine design.
Digital systems class at uni
Greatest Common Divisor calculator showcasing CPU-like controller + datapath architecture using subtraction-based Euclidean algorithm. Demonstrates synthesizable FSM design vs behavioral modeling trade-offs with complete hardware implementation.
This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments
This project implements a Finite State Machine (FSM) in Verilog to control a simple traffic light system.The design models real-world sequential logic using a Moore machine (outputs depend only on the current state).A testbench verifies the functionality by simulating clock cycles and observing the light outputs.
A single-person game of blackjack, playable on the Altera DE2-115 FPGA board. The game is designed in Verilog and resembles the Atari 2600 version of blackjack. It features a player-versus-computer mode, where the computer acts as the dealer. Contains a Linear Feedback Shift Register (LFSR) and a Finite State Machine (FSM).
Finite State Machine (FSM) designed to handle the movements of a Land Rover based on binary inputs. The FSM utilizes D flip-flops and combinatorial logic to transition between states and produce appropriate output signals for controlling the Land Rover's movement.