Dietmar Menden

Is There Still A Future For Hard Disk Drives? The cost of HDDs and SSDs will continue to fall, while capacity will continue to increase in both. The capacity for solid state drives (#SSDs) keeps going up while the price per terabyte keeps falling, sometimes raising questions about the future for hard disk drives (#HDDs). Will the cost of #SSDs per TB eventually become so low that they will totally displace HDDs? Barry Pangrle decided to ask a couple of experts in the field, Jim Handy from Objective Analysis and Thomas Coughlin of Coughlin Associates. He was looking for a comparison projection for HDDs and SSDs that would go about five years out into the future. Jim had performed such an exercise back in 2017, WDC: No SSD/HDD Crossover,but I needed something more recent. Jim had his SSD forecast data, shown in red in Figure 1 and Tom provided the HDD data shown in blue. The slope is steeper for the #SSD data, but it does not look like we’ll see a crossover in the next 5 years. The green $4.75/TB point was placed there by Barry to show readers where that falls on the plot and to use again later in another chart.... A very big thank you to Barry Pangrle , Jim Handy , Thomas Coughlin and Semiconductor Engineering for this very interesting full comparison/article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eKTxfR7P #semiconductorindustry #semiconductor #technology #tech #chip #chips #it #datacenter #technology #memory #storage #computer #ssd #hdd

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Automotive customers require solder joint inspection of IC packages mounted on PCBs to ensure they are reliably attached to the PCB. But solder joints of leadless Quad Flat No-Lead (QFN) packages are not visible and require the use of expensive X-Ray or labor-intensive manual inspection. "Wettable flanks" or "Plated End Leads" for QFN packages help form visible solder fillets that can be inspected using standard AOI (Automated Optical Inspection) equipment. For the AOI equipment to correctly detect and identify good vs bad solder wetting, the fillet height requirement is approximately 100 µm with a consistency of 1.67 Cpk. There are multiple options for wettable flank QFN packages: The first is called step-cut which is used for saw-singulated QFN packages. This can be applied to existing leadframe designs and involves an extra saw step prior to leadframe plating during assembly. The second option is dimpled leadframes. This is the wettable flank option typically used for punch-singulated QFN packages. The dimples are created during leadframe manufacturing. Dimpled leadframes can also be used for saw-singulated QFN packages, but if the lead pitch is <1mm, saw singulation causes burrs in the dimpled area of the leadframe. Hence, step-cut is a better option for saw-singulated QFNs with <1mm lead pitch. A third option in the industry is immersion tin plating where the QFN package first goes through its usual process flow. After package singulation, the units now have exposed copper flanks. The singulated units undergo additional processing prior to immersion tin plating to plate the exposed copper flanks. The tradeoffs with this option are the additional process, equipment requirements, and plating of units in singulated form. Download Amkor’s whitepaper on Wettable Flanks for Automotive Leadless Packages: https://lnkd.in/eht4JnpU

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Proud to reshare this milestone moment from Infineon — well done to all involved! Infineon has successfully completed the acquisition of Marvell Technology’s Automotive Ethernet business in an all‑cash transaction valued at $2.5 billion, officially closed on August 14, 2025. This strategic move dramatically strengthens Infineon’s automotive semiconductor leadership, particularly enhancing our microcontroller portfolio with Marvell’s Brightlane® Automotive Ethernet assets. The acquired business is expected to generate $225–250 million in 2025 revenue, with an impressive ~60% gross margin. It positions Infineon even more at the cutting edge of software-defined vehicles, enabling low-latency, high-bandwidth in‑vehicle networking. The integration of Ethernet at scale opens new horizons—think humanoid robots and advancing physical AI technologies. As Jochen Hanebeck noted, the strengthened alignment between “technology and business” continues to drive our ability to innovate across these dynamic domains. Congratulations to our teams and new colleagues—together, we’re building the future of mobility. #Infineon #Automotive #Ethernet #SoftwareDefinedVehicles #PhysicalAI #AutomotiveSemiconductors

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Microwave‑Enabled Atomic Layer Etch (ALE): Precision, Uniformity, Surface Integrity As devices scale into ever‑thinner films and challenging 3D architectures, the margin for error in etching is nearly gone. Semiconductor manufacturing now requires us to ask ourselves how precisely, how gently, and how predictably we can remove material at the atomic level. This is where Microwave Atomic Layer Etch (ALE) plays a transformative role, enabling removal through self‑limiting, sequential surface reactions that naturally enforce atomic‑scale control. Today, microwaves - at 2.45 GHz and 915 MHz - are strengthening ALE’s capabilities in fundamentally important ways. Why Microwaves Change the ALE Equation Traditional plasma sources must balance radical generation with ion bombardment, a trade‑off that becomes increasingly restrictive as stacks become more delicate. Microwave systems, however, offer a structural advantage: Microwave delivery → microwave plasma → radical generation → radical delivery Plasma is sustained off the chamber, allowing high radical density and very low ion at the wafer. - 2.45 GHz systems generate dense, stable plasmas suitable for high‑throughput radical production. - 915 MHz systems penetrate deeper and couple efficiently at lower pressures, ideal for uniformity over large wafer areas. The result is a decoupling of chemistry (radicals for the modification step) from physics (ion energy for activation). This improves control, reduces surface damage, and widens the process window for materials that were previously difficult to etch without structural or electrical degradation. Enabling Predictability Through In‑Situ Intelligence Microwave-enhanced ALE’s power is amplified when combined with in‑situ spectroscopic and reflectometry. This is more than just endpoint detection: it measures etch‑per‑cycle (EPC) in real time, ensuring each cycle removes only the intended amount. This combination of microwave‑driven radical delivery and cycle‑synchronous metrology provides: - Repeatable sub‑Ångström removal - Tight wafer‑to‑wafer and across‑wafer uniformity - Reduced sensitivity to chamber drift - Greater confidence in pattern fidelity for advanced designs As the industry pushes into new frontiers (power devices, advanced logic, memory architectures, and heterogeneous integration) the need for low‑damage, uniform, and metrology‑driven etch platforms keeps growing. Microwave‑enabled ALE offers a path that aligns with these demands: - Cleaner chemistries - Lower ion exposure - Higher uniformity across 200/300 mm - Atomic‑scale repeatability These strengths position microwave-ALE as a strategic capability for next‑generation semiconductor manufacturing and a key improvement over legacy plasma etch.

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🚀 What is FD-SOI and why does it matter? FD-SOI stands for Fully Depleted Silicon-On-Insulator. It’s a semiconductor wafer architecture where an ultra-thin silicon layer is built on top of an insulator (typically buried oxide). This structure reduces parasitic capacitance, improves performance, lowers leakage, and enables ultra-low-power designs—making it highly attractive for next-generation IoT, automotive, and RF applications. But FD-SOI isn’t easy to work with. The thin device layers and BOX (buried oxide) stack demand precision, clean edges, and zero thermal or mechanical stress during wafer processing. 💡 Where Synova comes in Synova’s Laser MicroJet (LMJ) combines a laser with a pressurized water jet, guiding the beam like an optical fiber. The water jet not only steers the beam but also cools and cleans simultaneously. For FD-SOI, this means: ✨ Stress-free cuts through thin silicon and oxide stacks ✨ No micro-cracks, chipping, or thermal damage ✨ High aspect-ratio features with smooth sidewalls ✨ Compatibility with sensitive device layers At Dynamic Process Group, Inc., we leverage this technology to micro-machine FD-SOI wafers for advanced R&D and production needs. Whether it’s resizing wafers, coring from specific regions, or creating custom geometries, LMJ allows us to handle even the most delicate SOI materials with unmatched precision. 🔍 FD-SOI is pushing the boundaries of semiconductor design. Synova’s LMJ is helping push the boundaries of how those materials can be shaped and prepared. #Semiconductors #FD-SOI #Synova #LaserMicroJet #WaferProcessing #Photonics

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Exciting news! Texas Instruments' TDA4 SDK 11.2 is coming this December with game-changing features for automotive ADAS and gateway designs: ✅ New Safety Toolkit with intuitive GUI for configuring diagnostics and automated code generation ✅ TÜV SÜD certified functional safety for C7x, MMA, and VPAC up to ASIL-B ✅ STL (software test library) to provide diagnostic coverage of hardware faults of the Cortex® A7, Cortex® R5F, and TI C7x processing cores ✅ Long-term support with 1 year of free bug fixes and development support. Accelerate your time-to-market while meeting safety requirements! #TexasInstruments #Automotive #FunctionalSafety #ADAS

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🔐 FPGA Frontrunner Event – FPGA Security in Focus FPGAs are powerful, adaptable — and increasingly exposed. As programmable logic moves into AI-enabled and data-intensive systems, security must extend across the entire lifecycle: bitstreams, firmware, IP, tools, runtime behaviour, and supply chain. Join us to explore emerging threats, real-world attack models, and proven mitigation strategies for securing FPGA-based systems. 🎤 Phill Payne (Novomorphic) True Random Numbers from a Quantum Computer — why real physical entropy changes secure system design. 🎤 Martin Thompson (ZF Group) Are FPGAs Unique for Security? — how programmable logic compares to MCUs and processors in security design. If you design, architect, regulate, or secure FPGA systems — this is for you. 🔗 Details & register: https://bit.ly/4rlRDiJ #FPGA #HardwareSecurity #CyberSecurity #EmbeddedSystems

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Almost twenty-six years in chip design teaches you to be skeptical of new tools. It’s easy to generate output; it’s much harder to generate trust. I held off on AI for three years for that reason. Then eight weeks ago, I started using it. Now, it's in almost every part of my working day. Two things have surprised me, pulling in opposite directions: 𝗧𝗛𝗘 𝗣𝗥𝗘𝗖𝗜𝗦𝗜𝗢𝗡 𝗪𝗜𝗡 When I describe a task carefully, the output is often exactly what I had in mind—and significantly faster than I could produce it. For someone who has spent over two decades writing specs and auditing complex designs, that lands differently. 𝗧𝗛𝗘 𝗥𝗘𝗩𝗜𝗘𝗪 𝗧𝗔𝗫 Sometimes it gives me so much, and so densely, that validating the output costs more time than the task would have taken from scratch. Reading and verifying a complex answer is its own form of engineering work. It doesn't disappear just because a machine produced it. 𝗧𝗛𝗘 𝗕𝗢𝗧𝗧𝗢𝗠 𝗟𝗜𝗡𝗘: The win is real, but so is the cost. I haven't settled on the right balance yet. Knowing when to reach for the tool, and when to just "do the thing" myself, feels like the actual skill being learned here. AI earns its place by being used well, not by being used everywhere. 𝗡𝗘𝗧-𝗡𝗘𝗧: I’m coming out ahead. By a lot. But the lesson isn't "use AI more." It's "use AI well." Here's the experiment I'm running on you right now: Can you tell whether I wrote this post, or whether AI did?

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🔋 The "Silicon Age" of Power Electronics Just Ended 🔋 January 2026 marks a turning point: Wide-bandgap semiconductors (GaN & SiC) have officially replaced silicon in high-performance power applications. The Breakthrough: Infineon just announced the world's first 300mm GaN production—delivering 2.3x higher chip yield than 200mm. Meanwhile, Vertical GaN architecture is achieving 30% efficiency gains and 50% smaller footprints in power supply units. Why This Matters: → Market exploding: $1.85B (2025) → $5.45B (2030) at 24% CAGR → 800V architectures now standard in EVs (7% range boost without bigger batteries) → AI data centers adopting 800V HVDC, cutting power losses by 12% → GaN/SiC solving dual crisis: AI's energy appetite + EV range anxiety The Shift: SiC = the "muscle" for high-voltage EV traction GaN = the "speed" for AI data center power supplies This isn't incremental improvement—it's material science fundamentally decoupling performance from energy consumption. The companies mastering wide-bandgap materials today are building the infrastructure backbone for the AI and EV era. What other material innovations do you see reshaping the semiconductor landscape? 📊 https://lnkd.in/dMbtVvSm #Semiconductors #PowerElectronics #GaN #SiC #MaterialScience #AI #ElectricVehicles #Innovation

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Chiplets are no longer a future concept, they’re becoming a present-day design reality. As designers move beyond monolithic scaling, interconnect complexity becomes a critical challenge. In this article, Clive Maxfield explores how proven NoC technology enables scalable, reusable multi-die systems that actually work in silicon. A valuable perspective on why the industry doesn’t need to wait to build chiplet-based designs 💡

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FYI UG1192: Introduction to AMD FPGA Design Flows for Altera Designers Link: https://lnkd.in/dfiKnEHA UG1192 is a must-have for any design team migrating from Altera to AMD platforms. It helps tackle every major migration pain point: architecture, toolchain, RTL, board design, clocking, SoC integration, and verification - while offering practical templates, reference flows, and in-depth conversion checklists. #amd #xilinx #userguide #fpga #designflow #fpgadesign #platforms #toolchain #RTL #boarddesign #clocking #soc #socintegration #verification #reference #conversion

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What are Active and Passive Components in Electronics? In electronics, components are broadly classified into two main categories: active and passive. The distinction lies in their ability to control current flow and their need for an external power source. 🚀 Active Components: Active components can control the flow of current in a circuit and often require an external power source to operate. They can introduce energy into the circuit, typically amplifying or switching electronic signals. 🔌 Function: Their primary functions include signal amplification, oscillation, and controlling current flow. They can provide power gain to a circuit. 🔌 Examples: Diodes: Allow current to flow in one direction only. Some types, like LEDs and laser diodes, also emit light. Transistors (Bipolar Junction Transistors - BJTs and Field-Effect Transistors - FETs): Used for amplification and switching of electronic signals. A small current or voltage at one terminal can control a larger current flow between other terminals. Integrated Circuits (ICs): Complex circuits fabricated on a single semiconductor chip. They can be analog (e.g., operational amplifiers), digital (e.g., microprocessors, memory chips), or mixed-signal. Thyristors and TRIACs: Semiconductor devices used for switching and controlling high electrical power. Power Sources (e.g., batteries, DC power supplies): Although sometimes considered separately, they actively supply energy to the circuit. 🚀 Passive Components: Passive components cannot control current flow using another electrical signal and do not require an external power source to operate. They cannot amplify signals; instead, they store, dissipate, or release energy. 🔌 Function: Their primary functions include energy storage (in electric or magnetic fields), current limitation, voltage division, and filtering of signals. 🔌 Examples: Resistors: Oppose the flow of electric current. They are used to limit current, divide voltage, and provide specific resistance in a circuit. Capacitors: Store electrical energy in an electric field between two conductive plates. They are used for filtering, energy storage, and coupling/decoupling AC and DC signals. Inductors (Coils): Store energy in a magnetic field when current flows through them. They are used for filtering, energy storage, and in resonant circuits.  Transformers: Transfer electrical energy between two or more circuits through electromagnetic induction. They are used to step up or step down AC voltages. For all semiconductor and AI related content, follow TechoVedas If you are looking to invest in semiconductors and need expert consulting, drop us a DM.

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InnoMux-2 flyback family of ICs for multi-output power supplies are a single-chip, single-stage solution that regulates output voltages and currents independently within ±3% accuracy, eliminating DC-DC converters, cutting component count by 50% and significantly reducing switching losses. https://okt.to/KACbPt #InnoMux #MultiOutput #PowiGaN

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𝗛𝗨𝗗𝗜𝗠𝗠𝘀 𝗷𝘂𝘀𝘁 𝗵𝗶𝘁 𝘁𝗵𝗲 𝗺𝗮𝗿𝗸𝗲𝘁 𝘄𝗶𝘁𝗵 𝗮 𝟱𝟬% 𝘁𝗵𝗿𝗼𝘂𝗴𝗵𝗽𝘂𝘁 𝗵𝗶𝘁 𝗰𝗼𝗺𝗽𝗮𝗿𝗲𝗱 𝘁𝗼 𝘀𝘁𝗮𝗻𝗱𝗮𝗿𝗱 𝗗𝗗𝗥𝟱. This is not a defect. It is the design. HUDIMMs (Hybrid Unbuffered DIMMs) use a single subchannel instead of the two-subchannel architecture that standard DDR5 relies on. The trade-off: lower cost, higher capacity per slot, but half the bandwidth per stick. The math matters here. Two HUDIMMs deliver the same throughput as one standard DIMM. So if you are building systems that need maximum memory capacity without hitting bandwidth ceilings, this could work. If you are building AI inference servers where memory bandwidth is already the constraint, this makes the problem worse. Tom's Hardware tested this in real configurations. The performance drop is measurable and consistent. The question is where this fits. Data center operators running memory-heavy but compute-light workloads might take the trade. AI training clusters will not. Anyone running inference on large models where memory speed determines latency will not. The cost savings have to be significant enough to justify the architectural compromise. We do not have pricing yet, but the performance penalty is clear. This is a tool for specific workloads, not a replacement for standard DDR5. The market will figure out fast where it belongs. Source Article: https://lnkd.in/g_wmm2Hk #DDR5 #Memory #DataCenter #AI #Infrastructure #ServerArchitecture #HirschReport

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Power intent is no longer a side note—it’s a design imperative. As SoCs grow in complexity, with chiplets, AI accelerators, and multi-voltage domains, verifying power strategies has become one of the most critical—and error-prone—challenges in the RTL-to-GDSII flow. Design teams are feeling the pressure. Without a consistent, scalable way to define and verify power intent, late-stage bugs, unpredictable silicon behavior, and costly respins are all too common. Teams need more than just a format—they need a methodology that scales with their ambition. That’s where Siemens EDA and UPF 4.0 come in. With Questa OneSim PowerAware, Siemens delivers a robust, production-proven solution to verify complex power strategies. From hierarchical power domains and DVFS modeling to advanced debug and emulation-driven power profiling, UPF 4.0—backed by Siemens tools—bridges the gap between intent and implementation. 🔗 Dive into the white paper to see how UPF 4.0 is transforming low-power verification: 👉 https://sie.ag/6eXVBs #UPF4.0 #SoCVerification #LowPowerDesign

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Is There a Place for SiC in Sub-200 W AC-DC / PFC Designs Dominated by SJ MOSFETs? In sub-200 W AC-DC and PFC applications, 650 V silicon superjunction (SJ) MOSFETs have long been the default choice. This is not because silicon still holds a material advantage, but because cost structures and established design ecosystems have historically locked out alternatives. If we assume cost parity between 700 V SiC MOSFETs and 650 V Si SJ devices, the basis for device selection changes. When Cost Is Fixed, Design Decisions Return to Device Behavior With cost removed as a differentiator, engineers naturally focus on system-level behavior: Temperature dependence of conduction losses Switching and recovery behavior under real operating conditions Long-term stability and consistency These factors define how much margin a design truly has beyond the datasheet. 650 V SJ Operates Near the Silicon Limit At breakdown voltages approaching 600–700 V, SJ MOSFETs already operate close to the practical limits of silicon. Further optimization relies on structural complexity rather than material margin, leading to strong temperature sensitivity and increased reliance on system-level compensation. This has largely been accepted because no alternative existed in the same cost range. Why the Transition Point Is 700 V SiC This is not about replacing 650 V SJ with 650 V SiC. The meaningful transition occurs when 700 V SiC replaces 650 V SJ. At 700 V, SiC remains well within its material comfort zone, retaining intrinsic margin in temperature behavior, switching dynamics, and long-term stress handling. This does not require a topology change or higher power—only a shift in where the device operates on the material curve. Redefining the Baseline Once cost parity is assumed, continuing to rely on silicon is no longer the default safe choice—it becomes a decision that requires justification. The question is no longer: Why use SiC below 200 W? It becomes: Why continue designing around silicon devices operating at their physical limit? Closing This is not about introducing SiC into low-power applications. It is about removing the need to design around silicon limits when a more tolerant material is available at the same cost level. I do have a 700 V SiC solution designed specifically for sub-200 W applications. If you’re interested in discussing this approach, feel free to contact me. #PowerElectronics #SiC #ACDCDesign #PFCDesign #HighVoltageMOSFET #SiliconLimits #SystemLevelDesign

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Design Insight — The Biggest Misconception About SiC & GaN — Why Performance Isn’t Enough, and Cost Structure Decides Who Wins Most discussions about SiC and GaN focus on performance — faster switching, cooler operation, higher efficiency. But after following real designs, failures, and wins across different markets, I’ve realized something important: Engineers admire performance. Markets approve cost structure. And this is the most common misunderstanding in power electronics. 1. Performance makes us excited. Cost makes decisions. Inside meetings, people love to say: “Efficiency improved by 2%.” “Hotspot dropped by 5–8°C.” “Switching is cleaner.” But when it comes to actual adoption, the real questions are always: “Can the overall BOM stay flat? Or better — can it go down?” If the answer is yes, performance becomes a bonus. If not, those specs stay in the datasheet. 2. The real SiC/GaN success stories all share one theme: subtraction. I’m not talking about papers or slides. I’m talking about real products already shipping. ✔ Mid-power supplies (≈250–400 W): Designs that needed two SJ MOSFETs in parallel now work with one SiC MOSFET — without increasing cost. ✔ High-frequency LED / industrial drivers: Higher switching speeds → smaller magnetics → simpler thermal → total system cost goes down. ✔ Compact power supplies: Architectures using 8–12 MOSFETs now redesigned with SiC/GaN to use half the devices. Across all of these cases, the reason is consistent: Not because performance is better — but because the cost structure becomes better. 3. The material-level myth: “Better performance means customers should pay more.” Some suppliers still believe: “My device is faster and cooler, so customers should accept a premium.” But honestly, the market doesn’t work like that. Power semiconductors are not luxury goods. You don’t get a premium just because you’re SiC or GaN. Customers care about: fewer devices smaller magnetics cheaper heatsinks smaller PCB simpler system lower BOM If you can’t solve these questions, your material — no matter how advanced — is just a high-cost option. 4. The real competitive edge isn’t the material — it’s the mindset. Across projects this year, I noticed a pattern: Teams that use new materials to enable “subtraction” are the ones winning designs. They change the design logic: fewer parts fewer magnetics less metal smaller layouts lower system cost Performance enables the subtraction. Cost structure enables adoption. 5. Final thought: technology shifts, but value doesn’t. Each year I feel this more strongly: Customers want more than we assume. And we can deliver more than we think. The value of SiC and GaN isn’t making systems more impressive — it’s making them more elegant. Not addition — subtraction. Not performance — cost structure. Not “because it’s SiC/GaN” but “because the whole system finally makes sense.” And honestly, this is just the beginning. #PowerElectronics #SiC #GaN #PowerDesign #MOSFET #EngineerInsight

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The MWCT2xx2A family delivers automotive-grade wireless charging with unmatched integration: ✅ AEC-Q100 Qualified ✅ Multi-protocol Qi support (EPP + MPP) ✅ App-ready controls: SPI, I²C, SCI ✅ Seamless integration for dashboards, consoles & headrests https://lnkd.in/g9cxKSr2 #AutoInnovation #NXP #WirelessCharging #MWCT2xx2A #ConnectedCar

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